MPEG1-Player in Java / Workshop Mensch-Computer-Vernetzung MPEG1-Player in Java

Wireless video systems have applications in cellular videophones, surveillance systems, and mobile patrols. The design of a wireless video system must consider two important constraints: low bit rate and low power dissipation. The ITU-T H.263 video codec standard is suitable for low bit rate wireless video systems, however it is computationally intensive. Some of the most computationally intensive operations in H.263 are the Discrete Cosine Transform (DCT) and the Inverse Discrete Cosine Transform (IDCT), which perform spatial compression and decompression of the data. In an ASIC implementation of H.263, the high computational complexity of the DCT and IDCT leads to high power dissipation of the blocks. Low power design of the DCT and IDCT is essential in a portable wireless video system. This paper examines low power design techniques for DCT and IDCT circuits applicable for low bit rate wireless video systems. Five low power techniques are applied to baseline reference DCT and IDCT circuits. The techniques include skipping low energy DCT input, skipping all-zero IDCT input, low precision constant multipliers, clock gating, and a low transition data path. Gate-level simulations characterize the effectiveness of each technique. The combination of all techniques reduces average power dissipation by 95% over the baseline reference DCT and IDCT blocks. / Master of Science

<p>As integrated circuits get smaller, faster and can fit more functionality, more problems arise with wire delays and cross-talk. Especially when using global clock signals distributed over a large chip area. This thesis will briefly discuss a solution to this problem using the Globally Asynchronous Locally Synchronous (GALS) design path.</p><p>The goal of this thesis was to test the solution by modelling and partially implementing an MPEG-2 video decoder connected as a GALS system, using synchronous design tools. This includes design of the system in Simulink, implementing selected parts in VHDL and finally testing the connected parts on an FPGA. Presented in this thesis is the design and implementation of the system as well as theory on the MPEG-2 video decoding standard and a short analysis of the result.</p>

As integrated circuits get smaller, faster and can fit more functionality, more problems arise with wire delays and cross-talk. Especially when using global clock signals distributed over a large chip area. This thesis will briefly discuss a solution to this problem using the Globally Asynchronous Locally Synchronous (GALS) design path. The goal of this thesis was to test the solution by modelling and partially implementing an MPEG-2 video decoder connected as a GALS system, using synchronous design tools. This includes design of the system in Simulink, implementing selected parts in VHDL and finally testing the connected parts on an FPGA. Presented in this thesis is the design and implementation of the system as well as theory on the MPEG-2 video decoding standard and a short analysis of the result.

As semiconductor technology continues to scale, energy-efficiency and power consumption have become the dominant design limitations, especially, for embedded and portable systems. Conventional worst-case design is highly inefficient from an energy perspective. In this dissertation, we propose techniques for adaptivity at the architecture and circuit levels in order to remove some of these inefficiencies. Specifically, this dissertation focuses on research contributions in two areas: 1) the development of SRAM models and circuitry to enable an intra-array voltage island approach for dealing with large random process variation; and 2) the development of low-energy digital signal processing (DSP) techniques based on controlled timing error acceptance. In the presence of increased process variation, which characterizes nanometer scale CMOS technology, traditional design strategies result in designs that are overly conservative in terms of area, power consumption, and design effort. Memory arrays, such as SRAM-based cache, are especially vulnerable to process variation, where the penalty is a power and bit-cell increase needed to satisfy a variety of noise margins. To improve yield and reduce power consumption in large SRAM arrays, we propose an intra-array voltage island technique and develop circuits that allow for a cost-effective deployment of this technique to reduce the impact of process variation. The voltage tuning architecture makes it possible to obtain, on average, power consumption reduction of 24% iso-area in the active mode, and the leakage power reduction up to 52%, and, on average, of 44% iso-area in the sleep mode. Alternatively, bitcell area can be reduced up to 50% iso-power compared to the existing design strategy. In many portable and embedded systems, signal processing (SP) applications are dominant energy consumers. In this dissertation we investigate the potential of error-permissive design strategies to reduce energy consumption in such SP applications. Conventional design strategies are aimed at guaranteeing timing correctness for the input data that triggers the worst-case delay, even if such data occurs infrequently. We notice that an intrinsic notion of quality floor characterizes SP applications. This provides the opportunity to significantly reduce energy consumption in exchange for a limited signal quality reduction by strategically accepting small and infrequent timing errors. We propose both design-time and run-time techniques to carefully control the quality-energy tradeoff under scaled VDD. The basic philosophy is to prevent signal quality from severe degradation, on average, by using data statistics. We introduce techniques for: 1) static and dynamic adjustment of datapath bitwidths, 2) design-time and run-time reordering of computations, 3) protection of important algorithm steps, and 4) exploiting the specific patterns of errors for low-cost post-processing to minimize signal quality degradation. We demonstrate the effectiveness of the proposed techniques on a 2D-IDCT/DCT design, as well as several digital filters for audio and image processing applications. The designs were synthesized using a 45nm standard cell library with energy and delay evaluated using NanoSim and VCS. Experiments show that the introduced techniques enable 40~70% energy savings while only adding less than 6% area overhead when applied to image processing and filtering applications. / text

MPEG1-Player in Java / Workshop Mensch-Computer-Vernetzung MPEG1-Player in Java

Currently different types of transform techniques are used by different video codecs to achieve data compression during video frame transmission. Among them, Discrete Cosine Transform (DCT) is supported by most of modern video standards. The integer DCT (Int-DCT) is an integer approximation of DCT. It can be implemented exclusively with integer arithmetic. Int-DCT proves to be highly advantageous in cost and speed for hardware implementations. In particular, the 4x4 and 8x8 block size Int-DCTs have the increased applicability at the current multimedia industry because of their simpler implementation and better de-correlation performance for high definition (HD) video signals. In this thesis, we present a fast and cost-shared reconfigurable architecture to compute variable block size Int-DCT for four modern video codecs – AVS, H.264/AVC, VC-1 and HEVC (under development). Based on the symmetric structure of the transform matrices and the similarity in matrix operations, we have developed a generalized “decompose and share” algorithm to compute the 4x4 and 8x8 block size Int-DCT. The algorithm is later applied to those four video codecs. Our shared hardware approach ensures the maximum circuit reuse during the computation. The entire architecture is multiplier free and designed with only adders and shifters to minimize hardware cost and improve working frequency. Finally, the design is implemented on a FPGA and later synthesized in CMOS 0.18um technology to compare the cost and performance with existing designs. The results show significant reduction in hardware cost and meet the requirements of real time video coding applications.

<p>The goal of this project was to implement and compare Invere Discrete Cosine Transform using three methods i.e. by bit parallel, digit serial and bit serial. This application describes a one dimensional Discrete Cosine Transform by bit prallel method and has been implemented by 0.35 ìm technology. When implementing a design, there are several considerations like word length etc. were taken into account. The code was implemented using WHDL and some of the calculations were done in MATLAB. The VHDL code was the synthesized using Design Analyzer of Synopsis; power was calculated and the results were compared.</p>

<p>IDCT (Inverse Discrete Cosine Transform) is a common algorithm being used with image and sound decompression. The algorithm is a Fourier related transform which can occur in many different types like, one-dimensional, two-dimensional, three-dimensional and many more.</p><p>The goal with this thesis is to create a fast and low effect version of two-dimensional IDCT algorithm, where techniques as multiple-constant multiplication and subexpression sharing plus bit-serial and bit-parallel arithmetic are used.</p><p>The result is a hardware implementation with power consumption at 19,56 mW.</p>

The goal of this project was to implement and compare Invere Discrete Cosine Transform using three methods i.e. by bit parallel, digit serial and bit serial. This application describes a one dimensional Discrete Cosine Transform by bit prallel method and has been implemented by 0.35 ìm technology. When implementing a design, there are several considerations like word length etc. were taken into account. The code was implemented using WHDL and some of the calculations were done in MATLAB. The VHDL code was the synthesized using Design Analyzer of Synopsis; power was calculated and the results were compared.