Traditional transfer function of integrators have warping effect in high frequency, this isn¡¦t good for make filter circuit. In reference[3] they mention a new transfer function to improve this error, but we found that the design of the previous circuit doesn¡¦t conform to the new transfer function. In this thesis, a different structure of integrator is presented, it use the method of double sampling to realize the modified bilinear transfer function, in addition, we also add a grounded-gate amplifier to decrease the input impedance and dummy switch technique what can reduce the charge injection error, then we use the central circuit to make the second order bandpass filter. The proposed circuit employ Hspice to simulate and design the form of the circuit layout, then use TSMC 0.35£gm CMOS process to make chip. The sampling frequency is 10MHz, the central frequency is 1MHz, and the power consumption is 1.78mW.

This thesis is to design a DSP-based speed-sensorless driver for an induction motor. The driver schemed with closed loop constant V/F ratio is used as the speed control configuration, and a new integrator with adaptive compensation is derived to estimate motor speed. The developed driver with speed estimator has solved the problems of estimation deviation and stability which was occurred when designed by Indirectly Field Orientation Control method under low speed by 10% of rated speed. The experiments demonstrate the sensorless driver has performance of accuracy and efficiency for speed estimation when motor is operated under the circumstance of low speed range and parameter variation.

Abstract Due to the development and proliferation of information and communication technologies, people¡¦s daily lives are indispensably relied on these tools. Based on concepts of safety, energy conservation, convenience, and comfort, intelligent buildings¡¦ designs have gradually become the main stream of the present and future architectures. Taiwan introduced the idea of the intelligent building since 1989. With the push of the automatic idea of the building, the security and surveillance systems integrators had become the new popular industry and the competition of the industry is more and more fierce. Understanding the key successful factors objectively is important of making administrative decision to security and surveillance systems integrator managers. In view of this, this research adopts the expert focus group interview and analytic hierarchy process theory. The author interview 10 high-level experts of the security and surveillance systems integrators and 10 customer experts of intelligence building traders to develop a set of the key success factors appraisal procedure to the security and surveillance systems integrators for intelligent buildings. Based on enterprise factor, staffs factor, and products factor, the author calculate the ranks and weights of the criterion and sub-criterion of the key successful factors. This can offer the security and surveillance systems integrator managers for intelligent buildings to make administrative decision. The study chooses three companies as an example to do empirical study, and compares their advantage and performance of the key successful factors. The result of study finds as follows. In criterion, the most important is produce factor, the less is staffs factor, and the end is enterprise factor. In sub-criterion, the most important is staff's professional ability technology, the less are price, products diversification, and customize degree. In ranks and weights, the last are productions separately, organized scale, and popularity and impressions. The conclusion can offer the security and surveillance systems integrator managers for intelligent buildings to make administrative decision.

In this thesis, a MP3 audio decoder has been designed as System-on-a-Chip using hardware/software co-design techniques. The MP3 audio decoder was built on a fast prototyping platform as ARM Integrator. The hardware architecture was built on the LEON2 SoC architecture, which contained an open source SPARC-V8 architecture compatible processor and an AMBA bus. Because MP3 decoding process was very computation-intensive for software-only decoder to decode in real-time on the LEON2 architecture, an IMDCT and poly phase synthesis filter bank hardware combined core pre-designed as an AMBA compatible core from our lab was reused and integrated. Besides integrating the IP, the MP3 decoding process was changed to use integer calculations instead of floating-point ones. In order to fast prototype LEON2 successfully on ARM Integrator, some modification of the LEON2 SoC hardware architecture was also made for example adding FIFO, modifying the memory controller, etc.

Advances in machine autonomy hold great promise in advancing technology, economic markets, and general societal well-being. For example, the progression of unmanned air systems (UAS) research has demonstrated the effectiveness and reliability of these autonomous systems in performing complex tasks. UAS have shown to not only outperformed human pilots in some tasks, but have also made novel applications not possible for human pilots practical. Nevertheless, human pilots are still favored when performing specific challenging tasks. For example, transportation of suspended (sometimes called slung or sling) loads requires highly skilled pilots and has only been performed by UAS in highly controlled environments. The presented work begins to bridge this autonomy gap by proposing a trajectory optimization framework for operations involving autonomous rotorcraft with suspended loads. The framework generates optimized vehicle trajectories that are used by existing guidance, navigation, and control systems and estimates the state of the non-instrumented load using a downward facing camera. Data collected from several simulation studies and a flight test demonstrates the proposed framework is able to produce effective guidance during autonomous suspended load operations. In addition, variational integrators are extensively studied in this dissertation. The derivation of a stochastic variational integrator is presented. It is shown that the presented stochastic variational integrator significantly improves the performance of the stochastic differential dynamical programming and the extended Kalman filter algorithms. A variational integrator for the propagation of polynomial chaos expansion coefficients is also presented. As a result, the expectation and variance of the trajectory of an uncertain system can be accurately predicted.

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These recent events of H1N1 flu outbreak illustrate the potential ramifications of infectious diseases on modern society and how society responds to these threats. This thesis addresses the specific case of avian influenza in U.S. poultry production. By building an expected utility maximization model for integrators contracting with growers of varying bio-secure levels, one can investigate the relationship between the bio-secure choice of the poultry industry and their production performance. The model is empiricized using the Phoon, Quek, and Huang (PQH) simulation technique to conduct numerical analysis. The model selects the optimal percentage of bio-secure farms for the integrators to contract, output price reductions due to disease outbreak, and different probabilities of disease outbreak. Results allow the examination of whether alternative USDA/APHIS indemnification rules can sufficiently influence integrators willingness to improve their bio-security level.

På RISE (Research Institutes of Sweden) finns en betydande kalibreringsverksamhet där avdelningen för högspänning önskar utöka sin strömmätningskapacitet för AC strömmar vid kraftfrekvens upp till 10 000 A.   Syftet är att med hjälp av Rogowskiprincipen bygga en mätrigg för kalibrering av strömtransformatorer i fält. Med noggrannhet bättre än 100ppm och 100 µrad för strömmar upp till 10 000A.   Arbetet börjar med att konstruera mätriggen och går sedan över till att kontrollera och eventuellt förbättra Rogowskispolen samt dess integrator.   Den slutgiltiga konstruktionen byggdes i aluminium och är en ledare som omsluts av ett rör som agerar som återledare. Runt den innersta ledaren centreras Rogowskispolen. Spolens integrator fick konstrueras om för att minimera den påverkan på noggrannheten som en temperaturförändring orsakar på Rogowskispolen samt för att ge stabila svar inom önskat frekvensområde. Detta lyckades till stor del och även om vissa problem med temperaturökning och påverkan av den finns kvar. Utan att hunnit testa att mäta 10 000 A har andra tester gjorts och mätningarna visar att mätriggen kan förväntas prestera antingen med: lägre noggrannhet, lägre strömmar eller under kortare mättid än önskat. Med några framtida förbättringar förväntas den kunna uppfylla satta mål. / At RISE’s (Research Institutes of Sweden) department for measurements and technology is calibration a big part of the work, the unit for high voltage have a desire to expand their capabilities in measurements of AC currents at power frequency up to 10 000 A.    The objective is to with the Rogowski principle construct a measuring rig for calibration of current transformers at customer laboratories. With precision of at least 100 ppm and 100 µrad for currents up to 10 000 A.   The project starts with the design of the rig, then focus on tests and possible improvements of an already bought Rogowski coil and integrator.   The final construction was made in aluminum with a concentric design where the return conductor is a tube surrounding the main conductor which the Rogowski coil was centered around. The integrator to the coil were not good enough and a new one was made, which were optimized to minimize the impact of temperature changes and give stable response to a desired frequency spectrum.  To great extent the project was a success, even though some challenges remain. The temperature compensation was not fully optimized, and the temperature rise are still too high. Today the measuring system do measurements with high accuracy at lower currents and are expected to preform according to the objective if you take in consideration either: lower current, shorter time with current or a lower accuracy.

The majority of signals, that need to be processed, are analog, which are continuous and can take an infinite number of values at any time instant. Precision of the analog signals are limited due to influence of distortion which leads to the use of digital signals for better performance and cost. Analog to Digital Converter (ADC), converts the continuous time signal to the discrete time signal. Most A/D converters are classified into two categories according to their sampling technique: nyquist rate ADC and oversampled ADC. The nyquist rate ADC operates at the sample frequency equal to twice the base-band frequency, whereas the oversampled ADC operates at the sample frequency greater than the nyquist frequency. The sigma delta ADC using the oversampling technique provides high resolution, low to medium speed, relaxed anti-aliasing requirements and various options for reconfiguration. On the contrary, resolution of the sigma delta ADC can be traded for high speed operation. Data sampling techniques plays a vital role in the sigma delta modulator and can be classified into discrete time sampling and continuous time sampling. Furthermore, the discrete time sampling technique can be implemented using the switched-capacitor (SC) integrator and the switched-current (SI) integrator circuits. The SC integrator technique provides high accuracy but occupies a larger area. Unlike the SC integrator, the SI integrator offers low input impedance and parasitic capacitance. This makes the SI integrator suitable for low supply voltage and high frequency applications. From a detailed literature study on the multi-bit sigma delta modulator, it is analyzed that, theneeds a highly linear digital to analogue converter (DAC) in its feedback path. The sigma delta modulators are very sensitive to linearity of the DAC which can degrade the performance without any attenuation. For this purpose T.C. Leslie and B. Singh proposed a Hybrid architecture using the multi-bit quantizer with a single bit DAC. The most significant bit is fed back to the DAC while the least significant bits are omitted. This omission requires a complex digital calibration to complete the analog to digital conversion process which is a small price to pay compared to the linearity requirements of the DAC. This project work describes the design of High-Speed Hybrid Current modeModulator with a single bit feedback DAC at the speed of 2.56GHz in a state-of-the-art 65 nm CMOS process. It comprises of both the analog and digital processing blocks, using T.C. Leslie and B. Singh architecture with the switched current integrator data sampling technique for low voltage, high speed operation. The whole system is verified mathematically in matlab and implemented using signal flow graphs and verilog a code. The analog blocks like switched current integrator, flash ADC and DAC are implemented in transistor level using a 65 nm CMOS technology and the functionality of each block is verified. Dynamic performance parameters such as SNR, SNDR and SFDR for different levels of abstraction matches the mathematical model performance characteristics.