CRAFTERS (Constraint and Application Driven Framework for Tailoring Embedded Real-time System) project aims to address the problem of uncertainty and heterogeneity in a distributed system by providing seamless, portable connectivity and middleware. This thesis contributes to the project by investigating the techniques that can be used in a distributed real-time embedded system. The conclusion is that, there is a list of specifications to be meet in order to provide a transparent and real-time distributed system. This thesis has implemented a basic system that provides support of scalability, accessibility, fault tolerant and consistency. The system is tested in di_erent areas and it shows its potentials to be a well transparent real-time system. This built the basis for further development.

The increasing number of cores in both desktops and servers leads to a demand for efficient parallel algorithms. This project focuses on the fundamental collective operation reduce, which merges several arrays into one by applying a binary operation element wise. Several reduce algorithms are evaluated in terms of performance and scalability and a novel algorithm is introduced that takes advantage of shared memory and exploits load imbalance. To do so, the concept of dynamic pair generation is introduced which implies constructing a binary reduce tree dynamically based on the order of thread arrival, where pairs are formed in a lock-free manner. We conclude that the dynamic algorithm, given enough spread in the arriving times, can outperform the reference algorithms for some or all array sizes.

Proper traffic analysis is crucial for the development of network systems, services and protocols. Traffic analysis equipment is often based on costly dedicated hardware, and uses proprietary software for traffic generation and analysis. The recent advances in open source packet processing, with the potential of generating and receiving packets using a regular Linux computer at 10 Gb/s speed, opens up very interesting possibilities in terms of implementing a traffic analysis system based on open-source Linux. The pktgen software package for Linux is a popular tool in the networking community for generating traffic loads for network experiments. Pktgen is a high-speed packet generator, running in the Linux kernel very close to the hardware, thereby making it possible to generate packets with very little processing overhead. The packet generation can be controlled through a user interface with respect to packet size, IP and MAC addresses, port numbers, inter-packet delay, and so on. Pktgen was originally designed with the main goal of generating packets at very high rate. However, when it comes to support for traffic analysis, pktgen has several limitations. One of the most important characteristics of a packet generator is the ability to generate traffic at a specified rate. Pktgen can only do this indirectly, by inserting delays between packets. Moreover, the timer granularity prevents precise control of the transmission rate, something which severely reduces pktgen’s usefulness as an analysis tool. Furthermore, pktgen lacks support for receives ide analysis and statistics generation. This is a key issue in order to convert pktgen into a useful network analyser tool. In this paper, improvements to pktgen are proposed, designed, implemented and evaluated, with the goal of evolving pktgen into a complete and efficient network analysis tool. The rate control is significantly improved, increasing the resolution and improving the usability by making it possible to specify exactly the sending rate. A receive-side tool is designed and implemented with support for measurement of number of packets, throughput, inter-arrival time, jitter and latency. The design of the receiver takes advantage of SMP systems and new features on modern network cards, in particular support for multiple receive queues and CPU scheduling. This makes it possible to use multiple CPUs to parallelize the work, improving the overall capacity of the traffic analyser. A significant part of the work has been spent on investigating low-level details of Linux networking. From this work we draw some general conclusions related to high speed packet processing in SMP systems. In particular, we study how the packet processing capacity per CPUdepends on the number of CPUs. This work consists of minimal set of kernel patches to pktgen.

E-rekrytering är idag ett framgångsrikt verktyg för att rekrytera dem bäst lämpade för organisationen. Dessa verktyg växte fram under senare delen av 90-talet och används idag av alla stora företag. Verktygen har dock haft svårt att kunna etableras bland SME. Detta beror på att dessa organisationer ej kan finansiera dyra system, de har ej specifik kunskap om rekrytering samt att dem inte rekryterar lika ofta som större organisationer. Under 2000-talet växte internet med dess nyutvecklade teknologier vilket gjorde att e-rekrytering flyttades ut till webben mer eller mindre fullständigt. Studien grundades på en litteraturstudie som kompletterades av workshops samt intervjuer. Resultatet påvisade att vissa e-rekryteringsverktyg passade för SME samt att beroende på organisationen så kan man ta reda på vilka verktyg det behöver. Studien kan även dra slutsatsen att anledningen till att införskaffa e-rekryteringssystem är att skapar affärsnytta.

New systems have higher and higher requirements in terms of reliability, safety, power consumption and performance. To meet those requirements, a custom processor can be a solution. That is why Thales is developing a processor that includes many features that make its architecture different from common architectures of general-purpose processors. To become widely usable, a fully optimizing compiler is the cornerstone that leads to its success. While most of the existing compilers manage to deal with code optimization for general purpose processors, their efficiency can considerably decrease when optimizing code for a custom processor whose architecture differs from general purpose processors. A new compiler had to be developed to translate C source code into highly optimized assembly code that would be able to deal with this processor's abilities, such as DSP-like instructions, in the best way possible, while introducing key features necessary to meet the requirements of Thales' line of products. Code optimizations have been introduced and enhanced, using pattern detection, control flow analysis or peephole optimization. At the same time, new key features have been added to the compiler, such as a compilation report, built-in functions support, and also fixed-point representation support. Many of these resources were lacking in existing compilers, which brings a noticeable added value to this compiler. As the processor is still under development, tests were carried out using a VHDL simulation model of the processor designed specifically to test the entire platform. The set of tests focused both on general purpose applications, and also on data processing algorithms. The optimization of this compiler led to an 18.3% shorter execution time for the set of tests, while reducing the total program size by 13.1% at least. Moreover, important features that existing compilers are lacking, have been added to the compiler. It helped improving the user-friendliness of the pair compiler/processor and it has proven to be of great interest for programmers.

Heterogeneous network deployment has been advocated as a mean to enhance the performance of cellular networks, but at the same time heterogeneous deployments give rise to new interference scenarios which are not seen in homogeneous deployments. This report includes five studies pertaining heterogeneous network deployments which is based on simulations of LTE in high detail on the lower layer protocol stack. In the first study it is investigated if results from simulated systems with ideal deployments can be generalized to realistic low power node deployments, which is seen to be the case. Three heterogeneous network con gurations, speci ed by 3GPP, were compared to a macro-only system. It is observed that the gain from low power nodes is strongly connected to the distribution of UEs. If the UE distribution is uniform the UE throughput gain is below 100 % while if the UEs are highly clustered a UE throughput gain of 400 % is achieved. The configuration with uniform UE distribution was further analyzed and it was seen that in a low load system the average UE throughput gain from low power nodes is below 20 %. In a low loaded system with uniform UE distribution adding low power nodes is not a good way of enhancing the system performance. A study investigating the gain of low power node range extension showed that SINR problems arise if the range of the low power nodes is extended, however the system as a whole gets increased throughput. The same applies for UE throughput. The main reasons are macro layer offloading & reduced interference created by the macro layer. It is showed that if more low power nodes are added the UE throughput gain per low power node increases. It is also showed that a system with two range extended low power nodes outperforms a system with four low power nodes without range extension. Inter-low power node interference is seen not to be a problem in the simulated system configurations.

OpenFOAM, an open source industrial Computational Fluid Dynamics (CFD) tool, which contains dozens of simulation application inside. A traditional approach to accelerate physical simulation process is to employ more powerful supercomputer. However, It is bound to expense large amount of hardware resources. In recent years, parallel and distributed computing is becoming an efficient way to solve such computational intensive application. This thesis pick up the most used compressible reacting solver named dieselFoam as the research target. Through the analysis of code structure in solver equation and native MPI implementation in OpenFOAM, deploy two level parallelism structure on SMP cluster, which use Message Passing Interface (MPI) between each SMP nodes and OpenMP directives inside SMP node. The key idea is making use of feature of threads parallelism, reduce unnecessary MPI communication overhead, thereby achieve performance improvement. The experiment results demonstrate application speedup by our solution, also in good agreement with the theoretical study. Based on the potential candidates analysis and performance results, we can conclude that the hybrid parallel model is proper for the acceleration of OpenFOAM solver application compare to the native MPI ways. Also through the discussion of the thesis, provides some suggestion about the future improvement area.

Software Defined Radios (SDRs) are redefining the current landscape of wireless communications in both military and commercial sectors. The rapidly evolving capabilities of digital electronics are making it possible to execute significant amounts of signal processing on general purpose processors ratherthan using special-purpose hardware. As a consequence of the availability of SDR, applications can be used to implement flexible communication systems in an operating prototype within a very short time. However, the initial lack of standards and design rules leads to incompatibility problems when using products from different manufacturers. This problem is critical for the military and public safety sectors, for this reason the US Army was interested in SDR and carried out research into the specification of a common software infrastructure for SDR. This initiative started in the mid-1990s and evolved into the Software Communications Architecture (SCA). SCA is a non-proprietary, open architecture framework that allows a designer to design interoperable and platform independent SDR applications. At the same time the SCA framework, by abstracting the radio communication system, speeds up waveform development because developers no longer have to worry about hardware details. This thesis project uses OSSIE, an open source SCA implementation, to illustrate the process of developing a waveform. Today companies are exploiting open source solutions and investing money to evaluate and improve available technologies rather than developing their own solutions: OSSIE provides a working SCA framework without any license cost. OSSIE also provides some tools to develop SCA waveforms. Of course open source software comes with some limitations that a designer must take into account. Some of these limitations will be described for OSSIE (specifically the limited documentation and lack of libraries), along with some suggestions for how to reduce their impact. This thesis project shows in detail the development process for SCA waveforms in OSSIE. These details are examined in the course of successfully implementing a target waveform to enable the reader to understand the advantagies and disadvantages of this technology and to facilitate more people using OSSIE to develop waveforms. Although a waveform was successfully implemented there were unexpected issues with regard to the actual behavior of the waveform when implemented on the hardware used for testing. / QC 20100831

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WOOL is a C parallelization library developed at SICS by Karl-Filip Faxén. It provides the tools for developing fine grained independent task based parallel applications. This library is distinguished from other similar projects by being really fast and light; it manages to spawn and synchronize tasks in under 20 cycles. However, all software development frameworks which expose radically new functionality to a programming language, gain a lot by having a compiler to encapsulate and implement them. WOOL does not differ from this category. This project is about the development of a source-to-source compiler for the WOOL parallelization library, supporting an extension of the C language with new syntax that implements the WOOL API, transforming it and eventually outputting GNU C code. Additionally, this compiler is augmented with a wrapper script that performs compilation to machine code by using GCC. This script is configurable and fully automatic. The main advantage gained from this project is to satisfy the need for less overhead in software development with WOOL. The simplified syntax results in faster and more economical code writing while being less errorprone. Moreover, this compiler enables the future addition of many more features not applicable with the current state of WOOL as a library.