Fault-tolerance, which is a complement to fault prevention, is an effective method of achieving ultra-high reliability. By taking this approach fault free computation can be achieved despite the presence of fault in the system. In this thesis three new fault tolerant techniques are presented and their advantages over well known fault-tolerant strategies are shown. One of these new techniques achieves higher reliability than any other similar techniques presented in the literature. Generally fault-tolerant structures consist of four major blocks: the replicated modules, the disagreement and detection circuit, the switching circuit, and the voting mechanism. The most critical component in a fault-tolerant system is the voter because the final output of the system is computed by this component. This dissertation presents a new implementation for voters which reduces both the complexity and the occupied area on the chip. The structures of the three techniques developed in this work are such that the complexity of their switching mechanisms grows only linearly with the number of modules but the voting mechanism complexity increases significantly. This is a better approach than those schemes in which the switching complexity increases significantly and the voter's complexity remains constant or grows linearly with the number of modules because it is easier to implement a complex voter than a complex switch (voters have more regular structures). Extensive comparisons are made between different fault-tolerant techniques. A new reliability model is also developed for system reliability evaluation of the new designs. The results of these analyses are plotted, and the advantages of the new techniques are demonstrated. In the final part of the work an expert system is described which uses the knowledge acquired by these comparisons. This expert system is meant as a prototype of a component of a CAD tool which will act as an advisor on fault-tolerant techniques.

Cette thèse de doctorat s’inscrit dans la thématique de la fiabilité des circuits intégrés dans l’industrie de la microélectronique. Un circuit intégré peut être exposé à des agresseurs électriques potentiellement dangereux pendant toute sa durée de vie. Idéalement, les circuits devraient pouvoir encaisser ces excès d’énergie sans perdre leur fonctionnalité. En réalité, des défaillances peuvent être observées lors de tests de qualification ou en application finale. Il est donc dans l’intérêt des fabricants de réduire ces défaillances. Actuellement, il existe des circuits de protection sur puce conçus pour dévier l’énergie de ces agresseurs à l’écart des composants fragiles. Le terme anglophone Electrical Overstress (EOS) englobe tous les agresseurs électriques qui dépassent une limite au-delà de laquelle les composants peuvent être détruits. La définition de ce terme est traitée en détail dans la thèse. L’objectif de cette thèse est de comprendre le statut du sujet des EOS dans l’industrie. On propose ensuite une nouvelle méthodologie de caractérisation de circuits pour quantifier leur robustesse face à des formes d’onde représentatives présélectionnées. On propose également des solutions de circuits de protection sur puce que ce soit au niveau de nouveaux composants actifs ou au niveau de la conception des circuits électroniques de protection. Par exemple on propose un nouveau composant basé sur le thyristor qui a la capacité de s’éteindre même si la tension d’alimentation est présente sur l’anode. Une autre proposition est de désactiver les circuits de protection face aux décharges électrostatiques lorsque les puces sont dans un environnement où l’on est sur ou ces agresseurs ne présentent plus de danger. Finalement, des perspectives du travail de thèse sont citées. / This Ph.D. thesis concerns reliability issues in the microelectronics industry for the most advanced technology nodes. In particular, the Electrical OverStress (EOS) issue is studied. Reducing EOS failures in Integrated Circuits (ICs) is becoming more and more important. However, the EOS topic is very complex and involves many different causes, viewpoints, definitions and approaches. In this context, a complete analysis of the current status of the EOS issue is carried out. Then, the Ph.D. objectives can be defined in a clear way. In particular, robustness increase of on-chip protection structures and IC characterization against EOS-like aggressors are two of the main goals. In order to understand and quantify the behavior of ICs against these aggressors, a dedicated EOS test bench is put in place along with the definition of a characterization methodology. A full characterization and comparison is performed on two different Electro- Static Discharge (ESD) power supply clamps. After identifying the potential weaknesses of the promising Silicon-Controlled Rectifier (SCR) device, a new SCR-based device with a turn-off capability is proposed and studied thanks to 3-D Technology Computer-Aided Design (TCAD)simulation. Triggering and turn-off behaviors are studied, as well as its optimization. Finally, three different approaches are proposed for improving the robustness of the IC onchip protection circuits. They are characterized thanks to the EOS test bench which allows identifying their assets as well as their points of improvement.