Le cadre de cette étude se focalise sur le développement de protections contre les décharges électrostatiques (ESD) externes aux composants électroniques à protéger. Pour des raisons applicatives, ou l'encombrement devient une préoccupation majeure, ces protections ESD doivent répondre à des contraintes de taille toujours plus difficiles à satisfaire tout en gardant les mêmes performances en robustesse. Ce travail présente un nouveau concept de structure de protection ESD bidirectionnel basé sur une technologie industrielle originellement dédié à la réalisation de capacités à haute densité d'intégration. Le procédé technologique possède une étape de fabrication de tranchées profonde qui est mise à profit dans cette étude pour la réalisation de diodes tridimensionnelles. L'optimisation de la configuration de ces structure a été menée par une étude théorique à l'aide des outils de simulation TCAD afin de mieux appréhender le fonctionnement physique et d'apporter des règles de conception. De nombreux résultats expérimentaux sont présentés et des comparaisons seront également menées afin de quantifier l'apport de cette nouvelle technologie. La meilleure configuration permet de garantir une réduction de 25% de la taille des structures tout en garantissant un niveau de robustesse élevé. / As part of this study focuses on the development of external protection against electrostatic discharge (ESD) to the electronic components to protect. For many applicative reasons where taken area becomes a major concern, the ESD protection must meet size constraints increasingly difficult to satisfy while keeping the same performance in robustness. This work presents a new concept of bi-directional ESD protection structure based on industrial technology originally dedicated to achieving high-density integration capabilities. The technological process has a deep trench production step which is used in this study for the realization of three-dimensional diodes. Optimizing configuration of the structure was conducted by a theoretical study using TCAD simulation tools to better understand the physical functioning and provide design rules. Many experimental results are presented and comparisons will also be conducted to quantify the contribution of this new technology. The best configuration ensures a 25% reduction in the size of structures while ensuring a high level of robustness.

L'influence des radiations naturelles sur les composants électroniques est un sujet qui est bien connu des acteurs du spatial et de l'aéronautique. Il n'en va pas de même pour les industries des transports (automobile, ferroviaire) alors que la vulnérabilité des composants « au sol » est bien réelle.Avec le développement massif des véhicules hybrides/électriques, les composants de puissance à semi-conducteur tels les IGBT (Transistor Bipolaire à Grille Isolée) vont être utilisés en très grand nombre dans les convertisseurs d'énergie utilisés comme maillons de fonctions critiques. La fiabilité de ces composants, basés sur des technologies récentes, contrairement à ce qui est utilisé pour les applications spatiales, doit être assurée.Le travail de thèse s'inscrit dans ce cadre et vise à identifier les phénomènes de défaillances des IGBT, composants incontournables dans les systèmes de conversion de l'énergie avec l'outil de simulation TCAD. Leur fiabilité sera estimée pour l'environnement radiatif naturel au niveau du sol afin de déterminer les probabilités de défaillances au niveau du composant et, plus tard, au niveau du système. Après avoir appréhendé les mécanismes de destruction de ces technologies pour lesquelles peu de travaux ont été effectués, il s'agira de quantifier le risque auquel sont exposés les systèmes électroniques face à l'environnement radiatif au sol. Les travaux présentés dans ce manuscrit, constituent une première étape visant à comprendre les différents mécanismes de défaillance des composants de puissance vis-à-vis des effets singuliers. L'objectif recherché à plus lointaine échéance est de déterminer dans quelle mesure ces mécanismes physiques complexes peuvent être simplifiés afin d'ouvrir la voie au développement de modèles de prédiction compactes. Un tel développement pourrait permettre de faire parvenir les outils de prédiction dédiés aux composants de puissance à la même maturité que ceux développés pour l'électronique numérique. / The influence of natural radiation on electronic devices is a topic that is well-known in the space and aeronautics areas. This is not true for the transportation industries (automotive, rail) while the vulnerability of components in "ground" is real.With the massive development of hybrid/electric vehicles, power components such as semiconductor IGBT (Insulated Gate Bipolar Transistor) and power MOS (Metal Oxide Semiconductor) will be used in large numbers in the power converters used in critical functions. The reliability of these components, based on recent technology, contrary to what is used for space applications must be assured.This work is aimed to assess the sensitivity of the investigated power devices considered as the core of the systems on energy conversion and identify physical phenomena inducing failure triggering and understand the different failure mechanisms of power components toward single event effects using TCAD simulation tool. The long term objective is to simplify these complex physical processes in order to develop prediction compact models. Such a development could be useful to achieve prediction tools dedicated to power components at the same maturity levels as those developed for digital electronics.

<p>The development of computer aided design tools for devices and circuits has increased the interest for accurate transistor modeling in microwave applications. In the increasingly expanding wireless communication market, there is a huge demand for high performance RF power devices. The silicon LD- MOSFET transistor is dueto its high power performance is today widely used in systems such as mobile base stations, private branch exchanges (PBX), and local area networks (LAN) utilizing the bands between 0.9 to 2.5 GHz. </p><p>In this research we simulated LD-MOSFET transistor characteristics of the structure provided by Infineon technology at Kista, Stockholm. The maximum drain current obtained in the simulation was 400 mA at a gate voltage of 8 V. This value is somewhat higher than the measured one. This difference can be attributed to the parasitic effects since no parasitic effects were included in the simulations in the beginning. The only parasitic effect studied was by placing the source contact at the bottom of the substrate according to real commercial device. The matching between simulated and measured results were improved and maximum drain current was reduced to 300 mA/mm which was 30% higher than the measured drain current </p><p>The large signal RF simulations were performed in time-domain in our novel technique developed at LiU. This technique utilizes a very simple amplifier circuit without any passive components. Only DC bias and RF signals are applied to the gate and drain terminals, with the same fundamental frequency but with 180o phase difference. The RF signal at the drain acting as a short at higher harmonics. These signals thus also acted as an active match to the transistor. Large signal RF simulations were performed at 1, 2 and 3 GHz respectively. The maximum of drain current signal was observed at the maximum of drain voltage signal indicating the normal behavior of the transistor. At 1 GHz the output power was 1.25 W/mm with 63% of drain efficiency and 23.7 dB of gain. The out pout power was decreased to 1.15 W/mm and 1.1 W/mm at 2 and 3 GHz respectively at the same time the efficiency and gain was also decreased to 57% and 19 dB at 2 GHz and 51% and 15 dB at 3GHz respectively.</p>

The development of computer aided design tools for devices and circuits has increased the interest for accurate transistor modeling in microwave applications. In the increasingly expanding wireless communication market, there is a huge demand for high performance RF power devices. The silicon LD- MOSFET transistor is dueto its high power performance is today widely used in systems such as mobile base stations, private branch exchanges (PBX), and local area networks (LAN) utilizing the bands between 0.9 to 2.5 GHz. In this research we simulated LD-MOSFET transistor characteristics of the structure provided by Infineon technology at Kista, Stockholm. The maximum drain current obtained in the simulation was 400 mA at a gate voltage of 8 V. This value is somewhat higher than the measured one. This difference can be attributed to the parasitic effects since no parasitic effects were included in the simulations in the beginning. The only parasitic effect studied was by placing the source contact at the bottom of the substrate according to real commercial device. The matching between simulated and measured results were improved and maximum drain current was reduced to 300 mA/mm which was 30% higher than the measured drain current The large signal RF simulations were performed in time-domain in our novel technique developed at LiU. This technique utilizes a very simple amplifier circuit without any passive components. Only DC bias and RF signals are applied to the gate and drain terminals, with the same fundamental frequency but with 180o phase difference. The RF signal at the drain acting as a short at higher harmonics. These signals thus also acted as an active match to the transistor. Large signal RF simulations were performed at 1, 2 and 3 GHz respectively. The maximum of drain current signal was observed at the maximum of drain voltage signal indicating the normal behavior of the transistor. At 1 GHz the output power was 1.25 W/mm with 63% of drain efficiency and 23.7 dB of gain. The out pout power was decreased to 1.15 W/mm and 1.1 W/mm at 2 and 3 GHz respectively at the same time the efficiency and gain was also decreased to 57% and 19 dB at 2 GHz and 51% and 15 dB at 3GHz respectively.

abstract: This PhD thesis consists of three main themes. The first part focusses on modeling of Silver (Ag)-Chalcogenide glass based resistive memory devices known as the Programmable Metallization Cell (PMC). The proposed models are examined with the Technology Computer Aided Design (TCAD) simulations. In order to find a relationship between electrochemistry and carrier-trap statistics in chalcogenide glass films, an analytical mapping for electron trapping is derived. Then, a physical-based model is proposed in order to explain the dynamic behavior of the photodoping mechanism in lateral PMCs. At the end, in order to extract the time constant of ChG materials, a method which enables us to determine the carriers’ mobility with and without the UV light exposure is proposed. In order to validate these models, the results of TCAD simulations using Silvaco ATLAS are also presented in the study, which show good agreement. In the second theme of this dissertation, a new model is presented to predict single event transients in 1T-1R memory arrays as an inverter, where the PMC is modeled as a constant resistance while the OFF transistor is model as a diode in parallel to a capacitance. The model divides the output voltage transient response of an inverter into three time segments, where an ionizing particle striking through the drain–body junction of the OFF-state NMOS is represented as a photocurrent pulse. If this current source is large enough, the output voltage can drop to a negative voltage. In this model, the OFF-state NMOS is represented as the parallel combination of an ideal diode and the intrinsic capacitance of the drain–body junction, while a resistance represents an ON-state NMOS. The proposed model is verified by 3-D TCAD mixed-mode device simulations. In order to investigate the flexibility of the model, the effects of important parameters, such as ON-state PMOS resistance, doping concentration of p-region in the diode, and the photocurrent pulse are scrutinized. The third theme of this dissertation develops various models together with TCAD simulations to model the behavior of different diamond-based devices, including PIN diodes and bipolar junction transistors (BJTs). Diamond is a very attractive material for contemporary power semiconductor devices because of its excellent material properties, such as high breakdown voltage and superior thermal conductivity compared to other materials. Collectively, this research project enhances the development of high power and high temperature electronics using diamond-based semiconductors. During the fabrication process of diamond-based devices, structural defects particularly threading dislocations (TDs), may affect the device electrical properties, and models were developed to account of such defects. Recognition of their behavior helps us understand and predict the performance of diamond-based devices. Here, the electrical conductance through TD sites is shown to be governed by the Poole-Frenkel emission (PFE) for the temperature (T) range of 323 K ˂ T ˂ 423 K. Analytical models were performed to fit with experimental data over the aforementioned temperature range. Next, the Silvaco Atlas tool, a drift-diffusion based TCAD commercial software, was used to model diamond-based BJTs. Here, some field plate methods are proposed in order to decrease the surface electric field. The models used in Atlas are modified to account for both hopping transport in the impurity bands associated with high activation energies for boron doped and phosphorus doped diamond. / Dissertation/Thesis / Doctoral Dissertation Electrical Engineering 2017

Dans ce travail faisant partie du projet FUI COMET (AAP9), nous avons dans un premier temps réalisé volontairement des contaminations métalliques pour différents contaminants (Ni, Mo, Cr, Fe, Au) à des doses maîtrisées soit en surface par spin coating, soit dans le volume par implantation ionique de wafers de silicium. Puis divers composants (diodes, transistor MOS ...) ont été fabriqués sur ces plaquettes contaminées.Ensuit, pour bien étudier l’impact de la contamination métallique sur des performances des composants, des caractérisations électriques ont été menées sur ces échantillons : caractéristiques Courant-Tension I(V), Capacité-Tension C(V) et ZERBST. La contamination surfacique par le nickel a présenté un impact important sur la dégradation de la durée de vie de génération des porteurs minoritaires. L’étude des caractéristiques I(V) sur des échantillons implantés par le molybdène a révélé une augmentation nette du courant inverse d’une diode Schottky avec un effet de dose cohérent. Les nombreuses mesures électriques sur les dispositifs fabriqués dans l’industrie (procédé MOS) sur des wafers contaminés volontairement par dépôt en solution sur la surface de silicium de Ni, Mo et Cr juste avant le début du procédé de grille ont montré l’absence d’influence significative de dégradation des performances des composants.Enfin, le logiciel SYNOPSYS SENTAURUS TCAD a été utilisé pour développer des modèles spécifiques permettant de reproduire l’impact des contaminants métalliques sur les caractéristiques ou la fiabilité des composants. / In this work which is part of the FUI project COMET (AAP9), intentional metallic contaminations have been realized for different contaminants (Ni, Mo, Cr, Fe, Au) either on the surface of silicon wafers by a spin-coating technique or in the bulk of silicon wafers by ion implantation. Then various devices (diodes, MOS transistor ...) were fabricated on these wafers contaminated.Secondly, in order to study the impact of metallic contamination on the performance of devices, some electrical characterizations have been carried out on these samples: Current-voltage characteristics I(V), Capacitance-Voltage C(V) and ZERBST. Surface contamination by nickel resulted in a significant impact on the degradation of the generation lifetime of minority carriers. The study of the characteristics I(V) on implanted samples by molybdenum showed that the reverse current of a Schottky diode increased with the concentration of contamination. The numerous electrical measurements on devices manufactured in the industry (MOS process) on wafers which have been contaminated intentionally by deposition solution on the silicon surface of Ni, Mo and Cr before the MOS process showed the absence of significant influence of degradation on the performances of devices.Finally, the software SYNOPSYS Sentaurus TCAD was used to develop the models to reproduce the impact of metallic contaminants on the electrical characteristics or reliability of the devices.

SiGe HBTs are preferred for quantum computing (QC) readout circuits due to their high gain and speed as well as the integration with complementary metal-oxide-semiconductor (CMOS) technology. The device physics of SiGe HBTs at cryogenic temperatures (CT), like carrier scattering, carrier transport, high-injection effects were not systematically and physically investigated. Thus, a physical compact model for circuit simulation did not exist at the start of this thesis work. In this work, the measurement setup has been built for obtaining direct-current (DC) and small-signal characteristics from medium to high frequencies over a wide temperature range. The radio frequency (RF) power of network analyzer and integration time of source monitor units have been investigated to ensure the accuracy of the DC and small-signal measurement. The key electrical parameters of SiGe HBTs have been characterized. The temperature trend of the transfer current, base current, sheet resistance, depletion capacitance, and built-in voltage, zero-bias hole charge have been extensively demonstrated and physically analyzed. Based on the comprehensive investigation on the electrical parameters over a wide range of temperatures, the following work consists of two parts: (1) the existing analytical formulations for various electrical components have been compared for their validation, and (2) in case of evident discrepancies the physical origin has been analyzed and valid compact formulations have been derived. For the first part, different bandgap models have been compared and the Lin et al. model is used for both TCAD simulation and compact model due to its high accuracy over a wide temperature and easy normalization for compact model usage. Based on the normalized bandgap voltage model, the derived built-in voltage model has been verified utilizing measured value for three depletion regions, i.e., base-emitter, base-collector and collector-substrate junction. Because the temperature dependence of zero-bias depletion capacitance and hole charge is attributed to the built-in voltage, the temperature behaviors of capacitance and hole charge are well modeled by the existing formulations according to the comparison between calculation and measurement. For the second part, for various SiGe HBT components discrepancies between model and measurement have been identified and comprehensive studies have been conducted. Firstly, the measured sheet and contact resistances of various components reduce with decreasing temperatures and saturate as the temperature towards 0K, which cannot be modeled by a widely used single power-law model. A Matthiesen's rule based model, consisting of two scattering mechanisms with opposite temperature trend, agrees well with the measured values. Additionally, an extended power-law model with a linear term is deduced for backward compatibility and less parameters. Secondly, direct tunneling is supposed to be dominant for transfer current at cryogenic temperatures, and a comprehensive derivation of transfer tunneling current for SiGe HBT is demonstrated. Moreover, a pronounced downward bending effect in both base-emitter and base-collector currents becomes significant at high current density region with decreasing temperatures. A modified diode current model including high-injection effect is given. Additionally, the recombination current is relevant for base-collector current and has been considered in the model. Due to the different temperature trends of thermal conductivity of silicon from cryogenic to room temperature, the thermal resistance shows a bell-shape and a modified formulation has been derived. Moreover, the dependence on chuck temperature and power dissipation has been considered. Finally, the derived formulations have been implemented in the mainstream industry BJT/HBT compact model, HIgh CUrrent Model - Level 2 (HICUM/L2), and good agreement has been achieved with the measurement. / Silizium-Germanium (SiGe) Heterojunction-Bipolartransistoren (HBTs) werden aufgrund ihrer hohen Verstärkung und Geschwindigkeit sowie der Integration in die komplementäre Metall-Oxid-Halbleiter (CMOS)-Technologie für Ausleseschaltungen im Quantencomputer (QC) bevorzugt. Die Bauelemente Physik von SiGe-HBTs bei kryogenen Temperaturen (CT), wie z.B. Ladungsträgerstreuung, Ladungsträgertransport und Hochinjektionseffekte, wurde nicht systematisch und physikalisch untersucht. Daher gab es kein physikalisches Kompaktmodell für die Schaltungssimulation zu Beginn dieser Arbeit. In dieser Arbeit wurde der Messaufbau für Gleichstrom- und Kleinsignaleigenschaften von mittleren bis hohen Frequenzen über einen weiten Temperaturbereich aufgebaut. Die Radiofrequenz (RF)-Leistung des Netzwerkanalysators und die Integrationszeit der Source-Monitor-Einheiten wurden untersucht, um die Genauigkeit der Gleichstrom- und Kleinsignalmessung zu gewährleisten. Die wichtigsten elektrischen Parameter von SiGe HBTs wurden charakterisiert. Der Temperaturtrend des Transferstroms, des Basisstroms, der Schichtwiderstände, der Verarmungskapazitäten, der eingebauten Spannung und der Gleichgewicht-Lochladung wurde ausführlich demonstriert und physikalisch analysiert. Basierend auf der umfassenden Untersuchung der elektrischen Parameter über einen weiten Temperaturbereich besteht diese Arbeit aus zwei Teilen: (1) die bestehenden analytischen Formulierungen für verschiedene elektrische Komponenten wurden zu ihrer Validierung verglichen, und (2) im Falle von Abweichungen wurden die physikalischen Ursachen analysiert und gültige kompakte Formulierungen abgeleitet. Für den ersten Teil wurden verschiedene Bandgap-Modelle verglichen, wobei das Modell von Lin et al. für sowohl Technology Computer-Aided Design (TCAD) Simulation als auch das Kompaktmodell aufgrund seiner hohen Genauigkeit über einen großen Temperaturbereich und der einfachen Normierung im Kompaktmodell verwendet wurde. Auf der Grundlage des normaierten Bandlückenmodells wurde das abgeleitete eingebaute Spannungsmodell anhand von Messwerten für drei Verarmungsbereiche, d.h. Basis-Emitter-, Basis-Kollektor- und Kollektor-Substrat-Übergang, verifiziert. Da die Temperaturabhängigkeit der Verarmungskapazität und der Löcherladung auf die eingebaute Spannung zurückzuführen ist, wird das Temperaturverhalten der Kapazität und der Löcherladung gemäß dem Vergleich zwischen den Berechnungen und den Messungen durch die ausgearbeitete Formulierung gut modelliert. Im zweiten Teil wurden für verschiedene Komponenten des SiGe HBTs Abweichungen zwischen Modellen und Messungen identifiziert und umfassende Studien durchgeführt. Erstens nehmen die gemessenen Schicht- und Kontaktwiderstände verschiedener Komponenten mit abnehmender Temperatur ab und bleiben konstant mit der Temperatur in Richtung 0K, was nicht durch ein weit verbreitetes einfaches Power-Law-Modell modelliert werden kann. Ein auf der Matthiesenschen Regel basierendes Modell, das aus zwei Streumechanismen mit entgegengesetztem Temperaturtrend besteht, stimmt gut mit den gemessenen Werten überein. Zusätzlich wird ein erweitertes Power-Law-Modell mit einem linearen Term abgeleitet, um bei geriegerer Parameterzahl die Rückwärtskompatibilität zu gewährleisten. Zweitens wird angenommen, dass direktes Tunneln für den Transferstrom bei kryogenen Temperaturen dominant ist, und es wird eine umfassende Herleitung des Transfer-Tunnelstroms für SiGe HBTs. Drittens wird ein ausgeprägter Effekt sowohl bei den Basis-Emitter- als auch bei den Basis-Kollektor-Strömen im Bereich hoher Stromdichten mit abnehmender Temperatur signifikant. Es wird ein modifiziertes Diodenstrommodell angegeben, das den Hochinjektionseffekt berücksichtigt. Darüber hinaus ist der Rekombinationsstrom für den Basis-Kollektor-Strom von Bedeutung und wurde in dem Modell berücksichtigt. Viertens zeigt der Wärmewiderstand aufgrund des unterschiedlichen Temperaturverlaufs der Wärmeleitfähigkeit in Silizium von Tieftemperatur bis Raumtemperaturen eine Glockenkurve und es wurde eine modifizierte Formulierung abgeleitet. Außerdem wurde die Abhängigkeit von der Chuck-Temperatur und der Verlustleistung wurde berücksichtigt. Schließlich wurden die abgeleiteten Formulierungen in das branchenübliche Bipolartransistor (BJT)/HBT Kompaktmodell, HIgh CUrrent Model - Level 2 (HICUM/L2), implementiert, und es wurde eine gute Übereinstimmung mit der Messung erzielt. / 硅锗异质结双极晶体管(SiGe HBT)因其高增益、高速度以及与互补金属氧化物半导体(CMOS)技术的集成而成为量子计算(QC)读出电路的首选。极低温 (CT) 下 SiGe HBT 的器件物理特性，如载流子散射、载流子传输、高注入效应等，尚未得到系统的物理研究。因此，在本论文工作开始时，并不存在用于极低温下电路仿真的紧凑型物理模型。 在这项工作中，首先搭建立了极低温电学测量装置，用于在宽温度范围内获得直流(DC)和中高频率小信号特性。为确保直流和小信号测量的准确性，对矢网分析仪的射频功率和信号源测量单元(SMU)的积分时间进行了研究。对 SiGe HBT 的关键电气参数进行了表征。对传输电流、基极电流、薄膜电阻、耗尽电容、内建电压、零偏置空穴电荷的温度变化趋势进行了广泛的论证和物理分析。 基于对宽温度范围内电气参数的全面研究，以下工作由两部分组成：(1) 比较各种电气元件的现有解析公式，以验证其有效性；(2) 对于有明显差异的物理量分析其物理原因，并推导出有效的紧凑型。 在第一部分中，比较了不同的禁带温度模型，由于 Lin 等提出的模型在较宽温度范围内具有较高的精确度，而且易于归一化，因此被用于 TCAD 仿真和紧凑型模型。根据归一化禁带温度模型，利用三个耗尽区(即基极-发射极、基极-集电极和集电极-衬底交界处)的测量值验证了推导出的内建电压模型。由于零偏压耗尽电容和空穴电荷的温度依赖性归因于内建电压，因此根据计算和测量结果的比较，现有公式可以很好地模拟电容和空穴电荷的温度行为。 在第二部分中，针对各种 SiGe HBT 组分发现了模型与测量值之间的差异，并进行了全面研究。首先，测量到的各种组分的薄膜电阻和接触电阻随着温度的降低而减小，当温度接近 0K 时达到饱和，这无法用广泛使用的单一幂律模型来模拟。基于 Matthiesen 规则的模型由两种温度趋势相反的散射机制组成，与测量值非常吻合。此外，为了实现向前兼容和减少参数，还推导出一个带有线性项的扩展幂律模型。其次，在低温条件下，直接隧穿是传输电流的主导，因此对 SiGe HBT 的传输隧穿电流进行了全面推导。此外，随着温度的降低，在高电流密度区域，基极-发射极和基极-集电极电流都会出现明显的向下弯曲效应，由此包含高注入效应的修正二极管电流模型给出。此外，模型还考虑了与基极-集电极电流相关的复合电流。由于硅的热导率从低温到室温的温度变化趋势不同，热阻呈现钟形，因此得出了一个修正的公式。此外，还考虑了热阻受环境温度和功耗的相关性。 最后，推导的公式嵌入到工业界主流 BJT/HBT 紧凑型模型 HIgh CUrrent Model - Level 2 (HICUM/L2) 中，仿真结果与测量结果取得了良好的一致。

Despite significant advances in the field of organic electronic devices, a complete and thorough theoretical understanding of their operation is still missing. This study aims to deepen the understanding of the underlying physics of organic field-effect transistors (OFETs) through analytical modeling, numerical device simulations and experimental validations of contact-induced performance improvements and traps. The thesis presents a comprehensive methodology for reliable parameter extraction for the contact resistance of OFETs using conventional extraction methods originally developed for silicon-based transistors. A benchmarking strategy is proposed for accurate and reliable parameter extraction, involving a comparative study of different extraction techniques to ensure the most precise results. The study investigates the experimentally proven performance gain of OFETs with contact engineering on oxidized metal electrodes. Theoretical analysis is performed to identify the root causes of the observed performance enhancement, providing valuable insight into the underlying physics of contact engineering and its impact on OFET performance. In addition, the thesis explores the impact of dynamic trapping on highfrequency transistor performance and presents innovative methods for characterizing traps. Through the use of TCAD simulations, a comprehensive study of the internal quantities of organic transistors is conducted. The study provides a critical step towards developing a physics-based compact model for OFETs that can capture the essential physics of the device. Overall, this thesis provides comprehensive guidelines for reliable parameter extraction and performance improvement of OFETs. It makes significant contributions to the understanding of their underlying physics and lays the foundation for the development of physics-based compact models for OFETs, which could potentially revolutionize the field of organic electronics.

L’environnement radiatif spatial est particulièrement critique pour la fiabilité des circuits intégrés et systèmes électroniques embarqués. Cet environnement chargé en particules énergétiques (proton, électron, ions lourds, etc) peut conduire à des pannes transitoires (SET), ou permanentes (SEU) et dans certains cas destructives (type Latchup, SEL) dans les dispositifs embarqués. L'effet d'une seule particule est identifié comme un événement singulier (SEE). Les contraintes imposées par l'intégration technologique poussent les fabricants micro-électroniques à prendre en considération la vulnérabilité de leurs composants vis-à-vis du Latchup tout en considérant les phénomènes non destructifs tels que la corruption de données (SEU/MBU). Cette thèse est le fruit d'une collaboration entre l'ONERA et Sofradir, fabriquant électronique d'imageurs infrarouge. L'objectif de cette thèse est d'étudier les effets singuliers (SET/SEU/SEL) de la technologie CMOS utilisée par Sofradir dans des conditions de températures cryogéniques, et plus particulièrement l'effet Latchup. / The spatial radiative environment is particularly critical for the reliability of integrated circuits and embedded electronic systems. This environment loaded with energetic particles (proton, electron, heavy ions, etc.) can lead to transient (SET), or permanent (SEU) and insome cases destructive failures (Latchup, SEL) in embedded devices. The effect of a single particle is identified as a single event effect(SEE). The constraints imposed by technological integration push microelectronics manufacturers to consider the vulnerability of their components to Latchup while consideringnon-destructive phenomena such as data corruption (SEU/MBU). This thesis is the result ofcollaboration between ONERA and Sofradir, an electronic manufacturer of infrared imagers. The aim of this thesis is to study the singular effects (SET / SEU / SEL) of the CMOS technology used by Sofradir under cryogenic temperature conditions, and more particularly the Latchup effect.

La production d'énergie photovoltaïque est une option d'avenir pour répondre au développement économique de notre société tout en réduisant notre impact sur l'environnement. Mais pour devenir compétitive, cette filière doit améliorer le rendement des cellules solaires. Une technologie d'avenir consiste à combiner différents matériaux via une croissance par épitaxie et l'usage du collage direct. Cette thèse, financée par SOITEC, vise au développement du collage d'arseniure de gallium (GaAs) sur le phosphure d'indium (InP) pour la cellule SmartCell. L'objectif est d'optimiser son comportement électrique via un modèle numérique prenant en compte son état physico-chimique. Nous présentons d'abord un ensemble d'outils de caractérisations électriques pour réaliser une mesure I(V) précises de l'interface de collage. En fonction des cas, nous détaillons des contacts métalliques adaptés pour améliorer cette caractérisation. Une étude détaillée de l'hétérostructure GaAs/InP et des homostructures GaAs/GaAs et InP/InP amène ensuite à une compréhension de leur mécanisme de collage. Après recuit thermique, le procédé de collage hydrophile engendre des oxydes d'interfaces qui se résorbent dans le cas de l'InP et se fragmentent pour le GaAs. A paramètres constants, les empilements obtenus sont meilleurs que ceux de l'état de l'art au niveau électrique et mécanique. Nous poursuivons avec des propositions de procédés innovants pour maitriser l'oxyde d'interface et optimiser l'hétérostructure. Parmi ces options nous validons l'approche avec exposition ozone qui vise à générer sélectivement un oxyde avant mise en contact. L'empilement obtenu affiche une résistance proche de nos mesures de référence et a un fort potentiel. Enfin l'étude se conclue sur la présentation d'un modèle numérique inédit reliant procédé de collage, état d'interface et comportement électrique. A recuit donné, l'interface est hétérogène avec une zone reconstruite (conduction thermo-électronique) et une zone avec oxyde (conduction tunnel). Ces régions s'activent préférentiellement en fonction de la température de fonctionnement. Elles sont pondérés par un critère qui détermine le niveau de reconstruction du collage et qui sera utile pour de futurs développements de l'application. / The solar photovoltaic is a promising way to support our economical growth while it can reduce the environmental impact of our society. But, to be truly competitive, the sector has to develop more efficient solar cells. An interesting option aims at combining different materials either by epitaxy growth and direct bonding. The Ph.D. was funded by the SOITEC company with the goal to develop the bonding of the gallium arsenide (GaAs) on the indium phosphide (InP) for the SmartCell architecture. We had to optimize its electrical behavior with a numerical model taking into account the bonding interface state. We introduce the study with a wide range of I(V) tools to precisely characterize the bonding interface. Depending on the case, we detail suitable metal contacts to improve the test. A study in deep of the GaAs/InP heterostructure and the GaAs/GaAs and the InP/InP homostructures leads to a better understanding of the bonding mechanisms. After a thermal annealing, the hydrophilic bonding process generates oxyde compounds at the interface which are absorbed in the InP case and are fragmented in the GaAs case. For given parameters, our stacks are electrically and mechanically better than the state of the art. Then we propose innovative processes to control the interface oxyde and thus optimize the heterostructure. Among them, we validate a new approach with ozone exposure that selectively generates an oxyde prior to bonding. The interface resistance of the stack is therefore closed to our best results and has great potentials. To conclude, the study focuses on a novel numerical model connecting the bonding process, the interface state and the electrical behavior. For a given annealing, the interface is heterogenous with reconstructed areas (thermionic conduction) and oxyde areas (tunnel conduction). These regions are preferentially activated as a function of the operating temperature. They are weighted by a criteria determining the level of the bonding reconstruction which will be useful for the future developments of the application.