Dynamic logic circuits are highly suitable for high-speed applications, considering the fact that they have a smaller area and faster transition. However, their application in space or other radiation-rich environments has been significantly inhibited by their susceptibility to radiation effects. This work begins with the basic operations of dynamic logic circuits, elaborates upon the physics underlying their radiation vulnerability, and evaluates three techniques that harden dynamic logic from the layout: drain extension, pulse quenching, and a proposed method. The drain extension method adds an extra drain to the sensitive node in order to improve charge sharing, the pulse quenching scheme utilizes charge sharing by duplicating a component that offsets the transient pulse, and the proposed technique takes advantage of both. Domino buffers designed using these three techniques, along with a conventional design as reference, were modeled and simulated using a 3D TCAD tool. Simulation results confirm a significant reduction of soft error rate in the proposed technique and suggest a greater reduction with angled incidence. A 130 nm chip containing designed buffer and register chains was fabricated and tested with heavy ion irradiation. According to the experiment results, the proposed design achieved 30% soft error rate reduction, with 19%, 20%, and 10% overhead in speed, power, and area, respectively.

The power consumption of Static Random Access Memory (SRAM) has become an important issue for modern integrated circuit design, considering the fact that they occupy large area and consume significant portion of power consumption in modern nanometer chips. SRAM operating in low power supply voltages has become an effective approach in reducing power consumption. Therefore, it is essential to experimentally characterize the single event effects (SEE) of hardened and unhardened SRAM cells to determine their appropriate applications, especially when a low supply voltage is preferred. In this thesis, a SRAM test chip was designed and fabricated with four cell arrays sharing the same peripheral circuits, including two types of unhardened cells (standard 6T and sub-threshold 10T) and two types of hardened cells (Quatro and DICE). The systems for functional and radiation tests were built up with power supply voltages that ranged from near threshold 0.4 V to normal supply 1 V. The test chip was irradiated with alpha particles and heavy ions with various linear energy transfers (LETs) at different core supply voltages, ranging from 1 V to 0.4 V. Experimental results of the alpha test and heavy ion test were consistent with the results of the simulation. The cross sections of 6T and 10T cells present much more significant sensitivities than Quatro and DICE cells for all tested supply voltages and LET. The 10T cell demonstrates a more optimal radiation performance than the 6T cell when LET is small (0.44 MeV·cm2/mg), yet no significant advantage is evident when LET is larger than this. In regards to the Quatro and DICE cells, one does not consistently show superior performance over the other in terms of soft error rates (SERs). Multi-bit upsets (MBUs) occupy a larger portion of total SEUs in DICE cell when relatively larger LET and smaller supply voltage are applied. It explains the loss in radiation tolerance competition with Quatro cell when LET is bigger than 9.1 MeV·cm2/mg and supply voltage is smaller than 0.6 V. In addition, the analysis of test results also demonstrated that the error amount distributions follow a Poisson distribution very well for each type of cell array.

Os efeitos da radiação ionizante em dispositivos eletrônicos é uma preocupação crescente na tecnologia de semicondutores, especialmente devido à contínua redução dos dispositivos e ainda maior, quando são destinados para uso em ambientes agressivos com alta radiação, tais como missões espaciais, aceleradores de partículas ou reatores nucleares. Dentre os vários efeitos causados pela radiação ionizante em dispositivos eletrônicos está aquele devido à Dose Acumulada (Total Ionizing Dose - TID), o qual a acumulação de danos de radiação no dispositivo muda seu funcionamento normal. O TID causado por fótons em transístores já foi estudado no Brasil, mas o efeito de prótons num transistor bipolar, apresentado neste trabalho é um trabalho pioneiro no país. As curvas características de um transistor 2N3733 foram medidas antes, durante e após a irradiação de prótons entre 1,5 e 3,8 MeV, para quantificar as alterações das especificações elétricas do dispositivo. Nestas energias, há uma correlação direta entre a mudança na resposta elétrica e a energia do próton, exceto em algumas energias específicas, onde o pico de Bragg ocorreu perto das junções ou no meio do cristal de silício, demonstrando a importância da correta caracterização da camada de passivação em estudos de TID em dispositivos eletrônicos. A recuperação dos transistores irradiados após o recozimento a 50°C durante 8 horas também foi maior para aqueles irradiados nessas energias. Existe um limite superior de dose para o qual não foi observada alteração significativa do transistor. Este limite, da ordem de Grad, excede a maioria das aplicações em ambientes terrestres, mas está dentro do intervalo esperado para missões espaciais a Júpiter ou em grandes aceleradores de partículas. / The effect of ionizing radiation on electronic devices is a growing concern in semiconductor technology, especially due to the continuous reduction of the devices and even greater when they are intended for use in aggressive environments with high radiation, such as space missions, particle accelerators or nuclear reactors. Among the various effects caused by ionizing radiation on electronic devices are the effects due to Total Ionizing Dose (TID), in which the accumulation of radiation damage in the device changes its normal functioning. The TID caused by photons has already been studied in Brazil, but the effect of protons on a bipolar transistor, presented in this work is a pioneer work in the country. The characteristic curves of a 2N3733 transistor were measured before, during and after proton irradiation between 1.5 and 3.8 MeV, to quantify changes of the electrical specifications of the device. At these proton energies, there is a direct correlation between the change in the electric response to the proton energy, except at some specific energies where the Bragg peak occurred near the junctions or in the middle of the silicon crystal, demonstrating the importance of the correct characterization of the passivation layer in TID studies of electronic devices. The recovery of transistors irradiated after annealing at 50 ° C for 8 hours was also higher for those irradiated at these energies. There is an upper dose limit for which no alteration of the transistor was observed. This limit, of the order of Grad, exceeds most applications in terrestrial environments, but is within the expected range for space missions to Jupiter or large particle accelerators.

L’environnement radiatif spatial est particulièrement critique pour la fiabilité des circuits intégrés et systèmes électroniques embarqués. Cet environnement chargé en particules énergétiques (proton, électron, ions lourds, etc) peut conduire à des pannes transitoires (SET), ou permanentes (SEU) et dans certains cas destructives (type Latchup, SEL) dans les dispositifs embarqués. L'effet d'une seule particule est identifié comme un événement singulier (SEE). Les contraintes imposées par l'intégration technologique poussent les fabricants micro-électroniques à prendre en considération la vulnérabilité de leurs composants vis-à-vis du Latchup tout en considérant les phénomènes non destructifs tels que la corruption de données (SEU/MBU). Cette thèse est le fruit d'une collaboration entre l'ONERA et Sofradir, fabriquant électronique d'imageurs infrarouge. L'objectif de cette thèse est d'étudier les effets singuliers (SET/SEU/SEL) de la technologie CMOS utilisée par Sofradir dans des conditions de températures cryogéniques, et plus particulièrement l'effet Latchup. / The spatial radiative environment is particularly critical for the reliability of integrated circuits and embedded electronic systems. This environment loaded with energetic particles (proton, electron, heavy ions, etc.) can lead to transient (SET), or permanent (SEU) and insome cases destructive failures (Latchup, SEL) in embedded devices. The effect of a single particle is identified as a single event effect(SEE). The constraints imposed by technological integration push microelectronics manufacturers to consider the vulnerability of their components to Latchup while consideringnon-destructive phenomena such as data corruption (SEU/MBU). This thesis is the result ofcollaboration between ONERA and Sofradir, an electronic manufacturer of infrared imagers. The aim of this thesis is to study the singular effects (SET / SEU / SEL) of the CMOS technology used by Sofradir under cryogenic temperature conditions, and more particularly the Latchup effect.

Os efeitos da radiação ionizante em dispositivos eletrônicos é uma preocupação crescente na tecnologia de semicondutores, especialmente devido à contínua redução dos dispositivos e ainda maior, quando são destinados para uso em ambientes agressivos com alta radiação, tais como missões espaciais, aceleradores de partículas ou reatores nucleares. Dentre os vários efeitos causados pela radiação ionizante em dispositivos eletrônicos está aquele devido à Dose Acumulada (Total Ionizing Dose - TID), o qual a acumulação de danos de radiação no dispositivo muda seu funcionamento normal. O TID causado por fótons em transístores já foi estudado no Brasil, mas o efeito de prótons num transistor bipolar, apresentado neste trabalho é um trabalho pioneiro no país. As curvas características de um transistor 2N3733 foram medidas antes, durante e após a irradiação de prótons entre 1,5 e 3,8 MeV, para quantificar as alterações das especificações elétricas do dispositivo. Nestas energias, há uma correlação direta entre a mudança na resposta elétrica e a energia do próton, exceto em algumas energias específicas, onde o pico de Bragg ocorreu perto das junções ou no meio do cristal de silício, demonstrando a importância da correta caracterização da camada de passivação em estudos de TID em dispositivos eletrônicos. A recuperação dos transistores irradiados após o recozimento a 50°C durante 8 horas também foi maior para aqueles irradiados nessas energias. Existe um limite superior de dose para o qual não foi observada alteração significativa do transistor. Este limite, da ordem de Grad, excede a maioria das aplicações em ambientes terrestres, mas está dentro do intervalo esperado para missões espaciais a Júpiter ou em grandes aceleradores de partículas. / The effect of ionizing radiation on electronic devices is a growing concern in semiconductor technology, especially due to the continuous reduction of the devices and even greater when they are intended for use in aggressive environments with high radiation, such as space missions, particle accelerators or nuclear reactors. Among the various effects caused by ionizing radiation on electronic devices are the effects due to Total Ionizing Dose (TID), in which the accumulation of radiation damage in the device changes its normal functioning. The TID caused by photons has already been studied in Brazil, but the effect of protons on a bipolar transistor, presented in this work is a pioneer work in the country. The characteristic curves of a 2N3733 transistor were measured before, during and after proton irradiation between 1.5 and 3.8 MeV, to quantify changes of the electrical specifications of the device. At these proton energies, there is a direct correlation between the change in the electric response to the proton energy, except at some specific energies where the Bragg peak occurred near the junctions or in the middle of the silicon crystal, demonstrating the importance of the correct characterization of the passivation layer in TID studies of electronic devices. The recovery of transistors irradiated after annealing at 50 ° C for 8 hours was also higher for those irradiated at these energies. There is an upper dose limit for which no alteration of the transistor was observed. This limit, of the order of Grad, exceeds most applications in terrestrial environments, but is within the expected range for space missions to Jupiter or large particle accelerators.

Integrated Circuits in space suffer from reliability problems due to the radiative surroundings. High energy particles can ionize the semiconductor and lead to single event effects. For digital systems, the transients can upset the logic values in the storage cells which are called single event upsets, or in the combinational logic circuits which are called single event transients. While for analog systems, the transient will introduce noises and change the operating point. The influence becomes more notable in advanced technologies, where devices are more susceptive to the perturbations due to the compact layout. Recently radiation-hardened-by-design has become an effective approach compared to that of modifying semiconductor processes. Hence it is used in this thesis project. Firstly, three elaborately designed radiation-tolerant registers are implemented. Then, two built-in testing circuits are introduced. They are used to detect and count the single event upsets in the registers during high-energy particle tests. The third part is the pulse width measurement circuit, which is designed for measuring the single event transient pulse width in combinational logic circuits. According to the simulations, transient pulse width ranging from 90.6ps to 2.53ns can be effectively measured. Finally, two frequently used cross-coupled LC tank voltage-controlled oscillators are studied to compare their radiation tolerances. Simulation results show that the direct power connection and transistors working in the deep saturation mode have positive influence toward the radiation tolerance. All of the circuit designs, simulations and analyses are based on STMicroelectronics CMOS 90 nm 7M2T General Process.

Integrated Circuits in space suffer from reliability problems due to the radiative surroundings. High energy particles can ionize the semiconductor and lead to single event effects. For digital systems, the transients can upset the logic values in the storage cells which are called single event upsets, or in the combinational logic circuits which are called single event transients. While for analog systems, the transient will introduce noises and change the operating point. The influence becomes more notable in advanced technologies, where devices are more susceptive to the perturbations due to the compact layout. Recently radiation-hardened-by-design has become an effective approach compared to that of modifying semiconductor processes. Hence it is used in this thesis project. Firstly, three elaborately designed radiation-tolerant registers are implemented. Then, two built-in testing circuits are introduced. They are used to detect and count the single event upsets in the registers during high-energy particle tests. The third part is the pulse width measurement circuit, which is designed for measuring the single event transient pulse width in combinational logic circuits. According to the simulations, transient pulse width ranging from 90.6ps to 2.53ns can be effectively measured. Finally, two frequently used cross-coupled LC tank voltage-controlled oscillators are studied to compare their radiation tolerances. Simulation results show that the direct power connection and transistors working in the deep saturation mode have positive influence toward the radiation tolerance. All of the circuit designs, simulations and analyses are based on STMicroelectronics CMOS 90 nm 7M2T General Process.

Cette thèse s’intéresse aux effets des particules présentent naturellement dans l’atmosphère. L'étude se focalise principalement sur l'impact des neutrons sur des composants électroniques fortement intégrés. La première partie détaille l'environnement radiatif naturel ainsi que les moyens de tests existants. Les technique de test sous faisceau laser sont mise en avant. La seconde partie s’intéresse au développement d'une plateforme de test de mémoires à base de FPGA programmée en VHDL. Les conceptions matérielle et logicielle sont explicitées. Une plateforme de test pour microprocesseur est également présentée. La dernière partie traite de l'évaluation de la sensibilité d'une mémoire SRAM bulk 90 nm sous faisceau laser 1064 nm. Le décodage de son plan mémoire est effectué et des solutions de durcissement sont suggérées / This thesis highlights the effects of natural atmospheric particles. The study mainly focuses on the neutrons impact on highly integrated electronic component. The first part deals with the natural radiative environment and the tests facility. Laser beams facilities are point out. The second part explains the devlopment of a memory test platform which is based on a FPGA and programmed with VHDL. Hardware and software designs are detailed. A microprocessor test platform is presented too. The last part deals with the sensibility evaluation of a 90 nm bulk SRAM memory under a 1064 nm laser. The descrambling of the memory is explained and hardening solutions are proposed

Este trabalho apresenta uma avaliação da eficiência do dimensionamento e particionamento (folding) de transistores para a eliminação ou redução de efeitos de radiação. Durante o trabalho foi construído um modelo de transistor tipo-n MOSFET para a tecnologia 90nm, utilizando modelos preditivos. O transistor 3D modelado foi comparado com o modelo de transistor elétrico PTM level 54 da Arizona State University e os resultados mostraram uma coerência entre os dispositivos. Este transistor modelado foi irradiado por uma série de partículas que caracterizam ambientes terrestres e espaciais. Foi descoberto que a técnica de redimensionamento de transistores tem sua eficiência relacionada ao tipo de partícula do ambiente e não é aplicável em ambientes com partículas com alta energia. Descobriu-se também que aplicando o particionamento de transistores é possível reduzir a amplitude e a duração de erros transientes. A combinação do dimensionamento e o particionamento de transistores pode ser utilizada para a redução de efeitos de radiação incluindo partículas leves e pesadas. Por fim um estudo de caso foi realizado com uma célula de memória estática de 6 transistores utilizando as técnicas mencionadas anteriormente. Os resultados da célula de memória indicaram que a combinação das duas técnicas pode de fato reduzir e até impedir a mudança do estado lógico armazenado na célula. / In this work the transistor sizing and folding techniques were evaluated for SET robustness in a 90nm MOSFET technology using a 3D device model. A n-type MOSFET transistor using a 90nm technology predictive profile was modeled and functional behavior compared with PTM level 54 model showing a fit of the device with the PTM. During simulations the modeled device was irradiated in a simulation environment using particles with the profile of sea and space level ions. The radiation effects simulation had indicated that the transistor sizing can be more or less efficient to reduce SET according to the collected charge. It was found that for environments with high energy particle, transistor sizing was not able to reduce soft errors intensity. The use of folding has shown significant reduction of the amplitude and duration of the transient pulse, making this technique very useful to reduce soft errors. For alpha particles and heavy ions the combination of transistor folding and sizing had shown to be an effective combination to enhance the reliability of the circuits. A 6T SRAM cell was modeled to evaluate transistor sizing and folding techniques and the results confirmed the efficiency of folding plus sizing to reduce the effects of radiation.

Este trabalho apresenta uma avaliação da eficiência do dimensionamento e particionamento (folding) de transistores para a eliminação ou redução de efeitos de radiação. Durante o trabalho foi construído um modelo de transistor tipo-n MOSFET para a tecnologia 90nm, utilizando modelos preditivos. O transistor 3D modelado foi comparado com o modelo de transistor elétrico PTM level 54 da Arizona State University e os resultados mostraram uma coerência entre os dispositivos. Este transistor modelado foi irradiado por uma série de partículas que caracterizam ambientes terrestres e espaciais. Foi descoberto que a técnica de redimensionamento de transistores tem sua eficiência relacionada ao tipo de partícula do ambiente e não é aplicável em ambientes com partículas com alta energia. Descobriu-se também que aplicando o particionamento de transistores é possível reduzir a amplitude e a duração de erros transientes. A combinação do dimensionamento e o particionamento de transistores pode ser utilizada para a redução de efeitos de radiação incluindo partículas leves e pesadas. Por fim um estudo de caso foi realizado com uma célula de memória estática de 6 transistores utilizando as técnicas mencionadas anteriormente. Os resultados da célula de memória indicaram que a combinação das duas técnicas pode de fato reduzir e até impedir a mudança do estado lógico armazenado na célula. / In this work the transistor sizing and folding techniques were evaluated for SET robustness in a 90nm MOSFET technology using a 3D device model. A n-type MOSFET transistor using a 90nm technology predictive profile was modeled and functional behavior compared with PTM level 54 model showing a fit of the device with the PTM. During simulations the modeled device was irradiated in a simulation environment using particles with the profile of sea and space level ions. The radiation effects simulation had indicated that the transistor sizing can be more or less efficient to reduce SET according to the collected charge. It was found that for environments with high energy particle, transistor sizing was not able to reduce soft errors intensity. The use of folding has shown significant reduction of the amplitude and duration of the transient pulse, making this technique very useful to reduce soft errors. For alpha particles and heavy ions the combination of transistor folding and sizing had shown to be an effective combination to enhance the reliability of the circuits. A 6T SRAM cell was modeled to evaluate transistor sizing and folding techniques and the results confirmed the efficiency of folding plus sizing to reduce the effects of radiation.