Jiang, Mingqi. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2009. / Includes bibliographical references (leaves [49]-51). / Abstract also in Chinese. / Abstract --- p.i / Acknowledgement --- p.iii / Chapter 1 --- Introduction --- p.1 / Chapter 2 --- Rewiring Background --- p.4 / Chapter 2.1 --- REWIRE --- p.6 / Chapter 2.2 --- GBAW --- p.7 / Chapter 3 --- Retiming --- p.9 / Chapter 3.1 --- Min-Clock Period Retiming --- p.9 / Chapter 3.2 --- Min-Area Retiming --- p.17 / Chapter 3.3 --- Retiming for Low Power --- p.18 / Chapter 3.4 --- Retiming with Interconnect Delay --- p.22 / Chapter 4 --- Rewired Retiming for Flip-flop Reduction --- p.26 / Chapter 4.1 --- Motivation and Problem Formulation --- p.26 / Chapter 4.2 --- Retiming Indication --- p.29 / Chapter 4.3 --- Target Wire Selection --- p.31 / Chapter 4.4 --- Incremental Placement Update --- p.33 / Chapter 4.5 --- Optimization Flow --- p.36 / Chapter 4.6 --- Experimental Results --- p.38 / Chapter 5 --- Power Analysis for Rewired Retiming --- p.41 / Chapter 5.1 --- Power Model --- p.41 / Chapter 5.2 --- Experimental Results --- p.44 / Chapter 6 --- Conclusion --- p.47 / Bibliography --- p.50

Chau, Chun Pong. / "August 2010." / Thesis (M.Phil.)--Chinese University of Hong Kong, 2010. / Includes bibliographical references (leaves 67-71). / Abstracts in English and Chinese. / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Motivation --- p.1 / Chapter 1.2 --- Objectives --- p.4 / Chapter 1.3 --- Contribution --- p.4 / Chapter 1.4 --- Thesis Organization --- p.5 / Chapter 2 --- Background and Review --- p.6 / Chapter 2.1 --- Introduction --- p.6 / Chapter 2.2 --- Logic Cell Style and Mask Programmability --- p.6 / Chapter 2.3 --- CAD Tools Compatibility --- p.8 / Chapter 2.4 --- Summary --- p.9 / Chapter 3 --- Architectural Design --- p.11 / Chapter 3.1 --- Overview --- p.11 / Chapter 3.2 --- Programmable Layers --- p.12 / Chapter 3.3 --- Combinational Logics --- p.12 / Chapter 3.4 --- Sequential Logics --- p.19 / Chapter 3.5 --- Inter-cell Connections --- p.21 / Chapter 3.6 --- Hard Macros --- p.22 / Chapter 3.7 --- Summary --- p.22 / Chapter 4 --- Design Flow --- p.23 / Chapter 4.1 --- Overview --- p.23 / Chapter 4.2 --- Library Creation --- p.24 / Chapter 4.3 --- Synthesis --- p.30 / Chapter 4.4 --- Placement and Routing --- p.30 / Chapter 4.5 --- Static Timing Analysis --- p.34 / Chapter 4.6 --- Summary --- p.35 / Chapter 5 --- Experimental Results --- p.36 / Chapter 5.1 --- Benchmark Circuits Description --- p.36 / Chapter 5.2 --- Experiment Settings --- p.37 / Chapter 5.3 --- Ratio of Dedicated Elements --- p.42 / Chapter 5.4 --- Delay and Area Comparison --- p.49 / Chapter 5.5 --- Distributed Memories --- p.53 / Chapter 5.6 --- Summary --- p.54 / Chapter 6 --- Prototypes and Applications --- p.55 / Chapter 6.1 --- Overview --- p.55 / Chapter 6.2 --- First Prototype --- p.55 / Chapter 6.3 --- Second Prototype --- p.63 / Chapter 7 --- Conclusion --- p.65 / Chapter 7.1 --- Future Work --- p.66 / Chapter 7.2 --- Concluding Remark --- p.67

Chim, Fu Shing. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2008. / Includes bibliographical references (leaves 79-82). / Abstracts in English and Chinese. / Abstract --- p.i / Acknowledgement --- p.iii / Chapter 1 --- Introduction --- p.1 / Chapter 2 --- Rewiring Background --- p.4 / Chapter 2.1 --- ATPG-Based Rewiring - REWIRE --- p.5 / Chapter 2.2 --- Graph-Based Rewiring - GBAW --- p.7 / Chapter 3 --- Characteristics of Rewiring Algorithms --- p.10 / Chapter 3.1 --- Comparsion between GBAW and REWIRE --- p.10 / Chapter 3.2 --- Problem Definition and Motivation --- p.11 / Chapter 4 --- Expanding Pattern Library --- p.14 / Chapter 4.1 --- Optimizing GBAW's Pattern Library --- p.14 / Chapter 4.2 --- Reduced Function Set for Gates within Patterns --- p.15 / Chapter 4.3 --- Rewiring with Multiple-Input Gates --- p.15 / Chapter 4.4 --- Experiment with GBAW Rewiring --- p.18 / Chapter 4.4.1 --- Experimental Results --- p.18 / Chapter 4.4.2 --- Discussion --- p.19 / Chapter 4.5 --- Experiment with Multi-way GBAW Partitioning --- p.21 / Chapter 4.5.1 --- Experimental Results --- p.22 / Chapter 4.5.2 --- Discussion --- p.24 / Chapter 4.6 --- Summary --- p.24 / Chapter 5 --- Circuit Structure for Rewiring --- p.26 / Chapter 5.1 --- Common Circuit Structure in GBAW Patterns --- p.26 / Chapter 5.2 --- Single Fanout Chains and Reconverging Alternative Wires for REWIRE --- p.28 / Chapter 5.3 --- Successive Rewiring --- p.31 / Chapter 5.4 --- Summary --- p.33 / Chapter 6 --- Chain-Based Rewiring Approach --- p.35 / Chapter 6.1 --- Single Fanout Chains in Graph-Based Rewiring --- p.35 / Chapter 6.2 --- Chain-Based Rewiring Approach --- p.36 / Chapter 6.3 --- Experimental Results --- p.40 / Chapter 6.4 --- Discussion --- p.41 / Chapter 6.5 --- Summary --- p.43 / Chapter 7 --- Hybrid Rewiring Framework --- p.44 / Chapter 7.1 --- Limit of Static Approaches --- p.44 / Chapter 7.2 --- Analyzing Framework of Dynamic Rewiring --- p.45 / Chapter 7.3 --- Techniques for Redundancy Identification --- p.47 / Chapter 8 --- Hybrid Chain-Based Rewiring Approach --- p.53 / Chapter 8.1 --- Hybrid Rewiring Framework --- p.53 / Chapter 8.1.1 --- Chain-Based Preliminary Target Wire Filtering --- p.55 / Chapter 8.1.2 --- Implication-Based Candidate Wire Generation --- p.55 / Chapter 8.1.3 --- Fast Redundancy Identification --- p.57 / Chapter 8.2 --- Uncontrollability and Controlling-Value Paths --- p.58 / Chapter 8.3 --- HYBRID - An Implementation of Our Framework --- p.61 / Chapter 8.4 --- Experimental Results --- p.63 / Chapter 8.5 --- Discussion --- p.65 / Chapter 8.6 --- Summary --- p.67 / Chapter 9 --- Rewiring Coupled FPGA Technology Mapping --- p.68 / Chapter 9.1 --- FPGA Technology Mapping --- p.68 / Chapter 9.2 --- Rewiring Coupled FPGA Technology Mapping --- p.70 / Chapter 9.2.1 --- Rewiring-based Logic Level Reduction --- p.71 / Chapter 9.2.2 --- Incremental Logic Resynthesis (ILR) Area Minimization --- p.71 / Chapter 9.3 --- Experimental Results --- p.72 / Chapter 9.4 --- Discussion --- p.73 / Chapter 9.5 --- Summary --- p.75 / Chapter 10 --- Conclusion and Future Works --- p.76 / Bibliography --- p.79

Wong, Kak Yeung Alex. / Thesis submitted in: November 2007. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2008. / Includes bibliographical references (leaves 86-89). / Abstracts in English and Chinese. / Acknowledgement --- p.i / Abstract --- p.iii / 摘要 --- p.v / Table of contents --- p.vi / List of tables --- p.ix / List of Figures --- p.x / Chapter Chapter1 --- Introduction --- p.1 / Chapter 1.1 --- Background --- p.1 / Chapter 1.2 --- Motivation --- p.1 / Chapter 1.3 --- Summary of Contributions and Thesis Outline --- p.4 / Chapter Chapter 2 --- System Design and Architecture --- p.6 / Chapter 2.1 --- Architectural Consideration --- p.6 / Chapter 2.1.1 --- Previous work --- p.6 / Chapter 2.1.2 --- Proposed work --- p.10 / Chapter A) --- Transimpedance amplifier with off-chip component --- p.10 / Chapter B) --- Dual-loop transimpedance amplifier --- p.12 / Chapter 2.2 --- Design consideration for ultra low cutoff frequency filter --- p.13 / Chapter 2.2.1 --- Previous work on low cutoff frequency filter --- p.14 / Chapter A) --- GM-C with current division and sub-threshold operation --- p.14 / Chapter B) --- Capacitance Multiplier --- p.15 / Chapter C) --- Switched-opamp switched-capacitor (SO-SC) filter --- p.16 / Chapter 2.2.2 --- Proposed work for the ultra low cutoff frequency filter --- p.17 / Current steering lowpass filter --- p.17 / Chapter 2.1 --- Summary --- p.18 / Chapter Chapter 3 --- Transimpedance Amplifier Design --- p.21 / Chapter 3.1 --- Transimpedance amplifiEr with off-chip component --- p.21 / Chapter 3.1.1 --- Transimpedance amplifier with dc photocurrent rejection --- p.21 / Chapter 3.1.2 --- Proposed solution - Transimpedance amplifier with sample-and-hold in feedback --- p.23 / Chapter A) --- Operating principle --- p.23 / Chapter B) --- Simulation results --- p.25 / Chapter 3.2 --- Dual-loop transimpedance amplifier with DC photocurrent rejection --- p.27 / Chapter 3.2.1 --- Evolution from basic to proposed work --- p.27 / Chapter 3.2.2 --- Operating principle --- p.31 / Chapter 3.2.3 --- Development of the analytic model --- p.32 / Chapter 3.2.4 --- Derivation of frequency response --- p.37 / Chapter 3.2.5 --- Noise derivation --- p.40 / Total input referred noise --- p.43 / Chapter 3.3 --- Implementation and experimental results --- p.45 / Chapter 3.3.1 --- Off-chip capacitor TIA --- p.45 / Measurement results --- p.46 / Chapter 3.3.2 --- Dual-loop TIA --- p.49 / Measurement results --- p.51 / Chapter 3.4 --- Summary and comparison --- p.62 / Chapter Chapter 4 --- Ultra-Low Cutoff Frequency Filter Design --- p.65 / Chapter 4.1 --- Current-steering lowpass filter --- p.65 / Chapter 4.2 --- "Implementation, experimental and measurement results" --- p.67 / Chapter 4.2.1 --- Measurement results for CS-LPF --- p.68 / Chapter 4.2.2 --- Measurement results for overall system --- p.75 / Chapter 4.3 --- Summary --- p.82 / Chapter Chapter 5 --- Conclusions and Future Work --- p.84 / Chapter 5.1 --- Conclusions --- p.84 / Chapter 5.2 --- Future work --- p.85 / Bibliography --- p.86 / Appendix A Details about operation --- p.90 / Appendix B Complex pole derivation --- p.93 / Appendix C Details about noise derivation --- p.94 / Appendix D Details about sub-threshold operation --- p.98 / Appendix E (in CD-ROM) Transfer Function Derivation / Appendix F (in CD-ROM) Noise Transfer Function Derivation

Some people believe that IC densities are approaching the fundamental limits inherent to semiconductor technologies. One alternative to semiconductors is Quantum-dot Cellular Automata (QCA); QCA is a nanotechnology that offers the potential to build denser IC's that switch at higher frequencies and run on lower power. QCA's most basic building block, the QCA cell, is inherently binary; digital circuits are implemented by arranging these QCA cells in pre-defined configurations on a two dimensional plane. This paper proposes a logic formulation that describes arranging QCA cells on a two dimensional plane; it is presented as a set of rules that can be implemented with basic Boolean variables and operators. This Boolean formulation is general and can be applied to any given specification. In addition, an optimization constraint is defined so that the logic formulation will only validate the most efficient QCA cell arrangements. The correctness of the logic formulation has been empirically verified by testing it with a SAT solver. The effectiveness of the minimization constraint in conjunction with the logic formulation has been tested with a Pseudo-Boolean ILP solver.

A scalable macromodel for substrate noise coupling in lightly doped substrates with and without a buried layer has been developed. This model is based on Z-parameters and is scalable with contact size and separation. This model requires process dependent parameters that can be extracted easily from a small number of device simulations or measurements. Once these parameters are known, the model can be used for any spacing between the injecting and sensing contacts and for different contact geometries. The model is validated with measurements for a lightly doped substrate with a buried layer and predicts the substrate resistance values to within 12%. The substrate resistances obtained using the model are also in close agreement with the three-dimensional simulations for a lightly doped substrate. / Graduation date: 2003

Minimizing the dynamic power consumption of a circuit is becoming a more and more important issue for digital circuit design in the age of portable electronics. Among all the arithmetic circuits, addition is the most fundamental operation. Therefore, designing low power adder is an important and necessary research area. In this thesis, the dynamic switching power consumption of ripple carry adder, carry look ahead adder, carry skip adder, carry select adder, and prefix adder are discussed. The power factor, the sum of products of probability and fan-out of all internal nodes, is presented. This thesis also studies the power and time trade-off with efficiency index which is the product of power factor and worst case gate counts. The result shows that the carry look ahead adder has the lowest efficiency index in the design of a 64 bit adder. The carry skip adder is the best one in a design of a 16 and 32 bit adder. The ripple carry adder is the best choice for an 8 bit adder. This study also presents a low power prefix adder design which will reduce the power consumption of the prefix adder without lost of performance. / Graduation date: 1998

M.S. / Computer Science / Software has been developed to analyze the power requirements of NMOS integrated circuits. Power usage is calculated for the entire chip. Current flow through each metal segment of VDD and GND lines is also calculated. The program, Pwranal, takes CIF format files as input and analyzes DC power requirements in the IC. Power estimates are worst case numbers. Power requirements may be less than the estimate but will not be more. Heuristics based on circuit topology are used to generate a more refined estimate of power needs. Initial values of nodes can be specified to provide an even more refined worst case power estimate. Current density is calculated and warning messages are displayed when it exceeds safe values. Maximum voltage drop in the VDD and GND lines is also calculated. An output summary is sent to the terminal. An optional CIF format output file can also be generated that contains detailed information about power distribution within the circuit.

Graduation date: 1995

Graduation date: 1991