One of the major limiters to computer systems and systems on chip (SOC) designs is accessing the main memory, which is typically two orders of magnitude slower than the processor. To bridge this gap, modern processors already devote more than half of the on-chip transistors to the last-level cache. Caches have negative impact on area, power, and yield. This research goal is to design caches that operate at lower voltages while enhancing yield. Our strategy is to improve the static noise margin (SNM) and the writability of the conventional six-transistor SRAM cell by reducing the effect of parametric variations on the cell. This is done using a novel circuit that reduces the voltage swing on the word line during read operations and reduces the memory supply voltage during write operations. The proposed circuit increases the SRAM’s SNM and write margin using a single voltage supply that has minimal impacts on chip area, complexity, and timing. A test chip with an 8-kilobyte SRAM block manufactured in 45- nm technology is used to verify the practicality of the contribution and demonstrate the effectiveness of the new circuit’s implementation. Cache organization is one of the most important factors that affect cache design complexity, performance, area, and power. The main architectural choice for caches is whether to implement the tag array using a standard SRAM or using a content addressable memory (CAM). The choice made has far-reaching consequences on several aspects of the cache design, and in particular on power consumption. Our contribution in this area is an in-depth study of the complex tradeoffs of area, timing, power, and design complexity between an SRAM-based tag and a CAM-based one. Our results indicate that an SRAM-based tag design often provides a better overall design point and is superior with respect to energy, especially for interleaved multi-threading processors. Being able to test and screen chips is a key factor in achieving high yield. Most industry standard CAD tools used to analyze fault coverage and generate test vectors require gate level models. However, since caches are typically designed using a transistor-level flow, there is a need for an abstraction step to generate the gate models, which must be equivalent to the actual design (transistor level). The third contribution of the research is a framework to verify that the gate level representation of custom designs is equivalent to the transistor-level design. / text

Step-Flash Imprint Lithography (S-FIL[trademark]) is a low-cost, high-resolution, high-throughput pattern replication process with the potential to become the savior for the future of integrated circuit (IC) manufacturing where continued success ultimately depends on improvements in lithographic resolution. Traditional, optical lithography has driven projection imaging to its physical limits, and a new, disruptive lithography technique is needed for continued growth of the semiconductor industry. The revolutionary S-FIL process is based on the fast, in-situ polymerization of a liquid imprint material in contact with a high-resolution mold or template. The templates, fabricated by direct-write lithography, present the greatest expense when implementing an S-FIL process in manufacturing; therefore, the template lifetime must be maximized to distribute costs over a large number of products. Degradable cross-linking materials allow imprint resist contaminated templates to be cleaned without the risk of inorganic residues becoming lodged on the template surface. Cured imprint resist is insoluble in all non-reactive solvents due to its highly cross-linked structure. A polymer contaminate may be rendered soluble by degrading the cross-links and reducing the molecular weight. Several degradable cross-linker candidates were examined for compatibility with S-FIL processing and utility for wafer imprint reworking and template cleaning. The properties of the imprint resists formulated with degradable cross-linkers are reported. Tertiary ester and acetal containing moieties were di-functionalized with acrylate groups to form S-FIL compatible and acid degradable imprint precursors. Both ester and acetal cross-linkers are neat, low-viscosity ([less than or equal to] 20 cP) liquids at room temperature and are miscible with common imprint precursor components. Classical gel theory predicts that greater than 99% de-cross-linking reaction conversion is necessary to achieve solubility in a cured imprint resist formulation with 10 wt% degradable cross-linker. Concentrated sulfuric acid and heat was used to successfully strip tertiary ester cross-linkers from wafer and model template surfaces. Acetal cross-linkers were demonstrated to strip in the presence of trifluoroacetic acid at room temperature. Three-dimensional patterning is an integral benefit of S-FIL, which enables the streamlining of dual damascene processing with the use of multi-level templates. Multi-level imprint patterning allows the removal of over 100 unit process steps from the fabrication of interconnect structures in a modern IC chip. Multi-level S-FIL can be integrated into existing copper damascene interconnect fabrication using two different strategies. One technique requires an imprint resist and etch process for transferring multi-level imprints into an industry standard low-k dielectric. Some of the considerations for designing the multi-level resist and etch process are briefly described. The second strategy leverages the broad variety and flexibility of the imprint materials set, which is not available in photoresist materials technology. New “functional” imprint materials may be used with multi-level S-FIL to produce interconnect structures by directly imprinting an interlayer dielectric (ILD) precursor. The challenges associated with introducing new dielectric materials into a copper damascene process are presented. The design, processing, characterization and integration of novel materials is documented. Multi-level S-FIL with a directly patternable dielectric (DPD) enables low-cost fabrication of interconnect structures in an IC manufacturing back end of line. DPD’s based on either sol-gel or benzocyclobutane and acrylate functionalized polyhedral oligomeric silsesquioxanes show promise for integration as ILD’s based on sufficient thermal and mechanical properties. Electrical test vehicle integration with sol-gel formulated DPD’s shows promising yield of interconnect structures with vias ranging from 2 to 0.12 [mu]m. Examination of interconnect structure revealed an acceptable via profile and sufficient contact with metal one for integration in IC devices. / text

As process technologies continue their rapid advancement, transistor features are shrinking to almost unimaginable sizes. Some dimensions can be measured at the atomic level. One consequence of these smaller devices is that they have become more susceptible to deviations from nominal than previous process nodes. To illustrate, as few as one hundred atoms determine how much voltage is needed to turn a transistor on and off. With over two billion transistors on a single chip, it is easy to imagine how even the tiniest of variations can affect many transistors throughout the entire chip. To compensate for these deviations, chip designers add margin to their designs. Even more margin is then added for increased safety. All of this margin leads to chips that are slower than a nominal design would be. At the other end of the spectrum, these same deviations might result in chips that are faster than needed. However, faster is not always better, as these faster chips usually require more power. Even worse, these deviations sometimes produce chips that are both slower and use more power than a nominal design. TuneChip is designed to mitigate the effects of these process variations by speeding up areas of a chip that need to run faster while at the same time reducing power in parts of a chip that are operating faster than needed. TuneChip attacks the variation problem by changing the voltage on small areas of the chip in response to the type of variation for that particular area. Since voltage has a strong relationship to the speed of a chip, TuneChip can increase the speed of areas that need to go faster. At the same time, TuneChip can decrease the speed of other areas on the chip that are too fast. Even more important than speed for current designs, though, is power. Changing the voltage has a quadratic relationship with the amount of power consumed by that device. Specifically, a 10% reduction in supply voltage yields a 20% reduction in energy. Moreover, it is not only battery powered devices that benefit from reduced energy consumption; some high performance designs are limited by how much they can cool the chip. Cost-effective cooling technology is not scaling at anywhere near the same rate as transistor geometries. Reducing a chip’s power consumption also reduces excess heat. In order to selectively change the voltage of specific areas of the design, TuneChip starts by partitioning the chip into smaller blocks. A dual voltage design style with two voltage grids spans the entire chip. In order to best react to variations particular to an individual chip, each block is assigned a supply voltage only after manufacturing. First, the chip is tested at high voltage and high power in order to verify the correct functionality of that chip. If the chip passes its functionality testing, each individual block is tested to determine how fast it is operating. Blocks that need to run faster are configured to connect to the high supply voltage grid, and blocks that are able to run slower are configured to connect to the low supply voltage grid. The configurable block supply voltage connection is accomplished with pmos pass transistors that act like switches. By having only one pmos pass transistor switch turned on at a time, each block has a choice of two supply voltages. / text

As device geometries shrink, variability of process parameters becomes pronounced, resulting in a significant impact on the power and timing performance of integrated circuits. Deterministic optimization algorithms for power and area lack capabilities for handling uncertainty, and may lead to over-conservative solutions. As a result, there is an increasing need for statistical algorithms that can take into account the probabilistic nature of process parameters. Statistical optimization techniques however suffer from the limitation of high computational complexity. The objective of this work is to develop efficient algorithms for optimization of area and power under process variability while guaranteeing high yield. The first half of the dissertation focuses on two design-time techniques: (i) a gate sizing approach for area minimization under timing variability; (ii) an algorithm for total power minimization considering variability in timing and power. Design-time methods impose an overhead on each instance of the fabricated chip since they lack the ability to react to the actual conditions on the chip. In the second half of the dissertation we develop joint design-time and post-silicon co-optimization techniques which are superior to design-time only optimization methods. Specifically, we develop (i) a methodology for optimization of leakage power using design-time sizing and post silicon tuning using adaptive body bias; (ii) an optimization technique to minimize the total power of a buffer chain while considering the finite nature of adaptability afforded. The developed algorithms effectively improve the overconservatism of the corner-based deterministic algorithms and permit us to target a specified yield level accurately. As the magnitude of variability increases, it is expected that statistical algorithms will become increasingly important in future technology generations. / text

published_or_final_version / Electrical and Electronic Engineering / Doctoral / Doctor of Philosophy

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