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HARDWARE COMPILER DRIVEN HEURISTIC SEARCH FOR DIGITAL IC TEST SEQUENCES.Patel, Mayank Raman. January 1985 (has links)
No description available.
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Efficient backtracking strategies in test generationYu, Tein-Yow, 1961- January 1989 (has links)
This thesis addresses the problem of backtracking strategies in test generation. First, a methodology which uses status of absolute dominators as a means for causing backtracking during the test generation process is presented. Then, different heuristics that force the test generation to execute the backtracking procedure are investigated. Experiments which generated test patterns for over 30,000 faults have been used to evaluate these heuristics. According to the experimental results, we recommend a new backtracking strategy that has the best performance among the six strategies explored in this thesis.
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Pseudo-functional testing: bridging the gap between manufacturing test and functional operation.January 2009 (has links)
Yuan, Feng. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2009. / Includes bibliographical references (leaves 60-65). / Abstract also in Chinese. / Abstract --- p.i / Acknowledgement --- p.ii / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Manufacturing Test --- p.1 / Chapter 1.1.1 --- Functional Testing vs. Structural Testing --- p.2 / Chapter 1.1.2 --- Fault Model --- p.3 / Chapter 1.1.3 --- Automatic Test Pattern Generation --- p.4 / Chapter 1.1.4 --- Design for Testability --- p.6 / Chapter 1.2 --- Pseudo-Functional Manufacturing Test --- p.13 / Chapter 1.3 --- Thesis Motivation and Organization --- p.16 / Chapter 2 --- On Systematic Illegal State Identification --- p.19 / Chapter 2.1 --- Introduction --- p.19 / Chapter 2.2 --- Preliminaries and Motivation --- p.20 / Chapter 2.3 --- What is the Root Cause of Illegal States? --- p.22 / Chapter 2.4 --- Illegal State Identification Flow --- p.26 / Chapter 2.5 --- Justification Scheme Construction --- p.30 / Chapter 2.6 --- Experimental Results --- p.34 / Chapter 2.7 --- Conclusion --- p.35 / Chapter 3 --- Compression-Aware Pseudo-Functional Testing --- p.36 / Chapter 3.1 --- Introduction --- p.36 / Chapter 3.2 --- Motivation --- p.38 / Chapter 3.3 --- Proposed Methodology --- p.40 / Chapter 3.4 --- Pattern Generation in Compression-Aware Pseudo-Functional Testing --- p.42 / Chapter 3.4.1 --- Circuit Pre-Processing --- p.42 / Chapter 3.4.2 --- Pseudo-Functional Random Pattern Generation with Multi-Launch Cycles --- p.43 / Chapter 3.4.3 --- Compressible Test Pattern Generation for Pseudo-Functional Testing --- p.45 / Chapter 3.5 --- Experimental Results --- p.52 / Chapter 3.5.1 --- Experimental Setup --- p.52 / Chapter 3.5.2 --- Results and Discussion --- p.54 / Chapter 3.6 --- Conclusion --- p.56 / Chapter 4 --- Conclusion and Future Work --- p.58 / Bibliography --- p.65
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Reliability and test of high-performance integrated circuitsMohanram, Kartik 28 August 2008 (has links)
Not available / text
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Defect detection in semiconductor die imagesNg, Nga-yi, Ada., 伍雅怡. January 2005 (has links)
published_or_final_version / abstract / Electrical and Electronic Engineering / Master / Master of Philosophy
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AN ANALYSIS OF A MULTILAYER DISTRIBUTED RC-NETWORKRaghunath, Subramaniam, 1944- January 1974 (has links)
No description available.
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An integrated random bit generator for applications in cryptographyPetrie, Craig Steven 12 1900 (has links)
No description available.
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Analysis of fault coverage masking in built-in self-test schemesCotsapas, Nicos. January 1985 (has links)
No description available.
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Test support processor for enhanced testability of high performance integrated circuitsZhou, Qing 08 1900 (has links)
No description available.
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Signature based testing of analog and RF circuitsVoorakaranam, Ramakrishna 05 1900 (has links)
No description available.
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