No description available.

This paper discusses an intelligence driven test system for generation of test sequences for stuck-open faults in CMOS VLSI sequential circuits. The networks in system evaluation are compiled from an RTL representation of the digital system. To excite a stuck-open fault it is only necessary that the output of the gate containing the fault take on opposite values during two successive clock periods. Excitation of the fault must therefore constrain two successive input/present-state vectors, referred to in the paper as the pregoal and goal nodes respectively. An initialization procedure is used to determine the pregoal state. Two theorems are proved establishing a 1-1 correspondence between stuck-at and stuck-open faults. As a result the D-algorithm may be used to determine the goal node. Determining the nodes was tried on many circuits and a high success rate was achieved. The pregoal is observed to have more "don't care" values. The next step is a "sensitization search" for an input sequence (X(s)) that drives the memory elements to the determined pregoal and goal states over two consecutive clock periods. It is easier for the search to reach the pregoal due to the greater number of "don't cares." Following a "propagation search" for an input sequence (X(p)) to drive the effect of the fault to an external output, the sequence of vectors (X(s)), (X(p)) will be passed to an "ALL-Fault Simulator" for verification. The simulation will be clock mode but will represent the output retention resulting from the stuck-open faults. One measure of the value of a special search procedure for stuck-open faults can be obtained by comparing the results employing this search with results obtained by searching only for the analogous stuck-at faults. A first order prediction would be a likelihood less than 0.5 that the predecessor of a stuck-at goal node would excite an opposite output in the gate containing the fault. A comparison of the two methods using the stuck-open "All-Fault Simulator" is presented.

This dissertation describes a new simulation technique for an automatic test generation system, SCIRTSS version 4.0 (Sequential Circuit Test Sequence System). This test generation system is driven by the hardware compiler AHPL, a Hardware Programming Language, and an intelligent heuristic-based search for test vector generation. Using a fault-injection gate-level simulator and the generated test vector, all the faulty states of the circuit are simulated in parallel and the simulator is thus able to find all detected faults by a particular input sequence. The major objective of this research was to develop a faster replacement for the existing simulation process. The philosophy of divide and conquer is used in the development of the new simulation technique. Sequential networks are divided into combinational sub-networks, and, if necessary, the combinational sub-networks are further reduced into fan-out free regions. Thus, the problem is reduced to a relatively simple combinational one. In addition to the classical faults, the new simulator attempts to detect CMOS stuck-open faults. Several circuits were tested under SCIRTSS 4.0 using both the existing and the new simulation techniques. The results are listed in this paper to verify superiority of the new simulation technique.

For reliable digital communication between devices, the sources that contribute to data sampling errors must be properly modeled and understood. Clock jitter is one such error source occurring during data transfer between integrated circuits. Clock jitter is a noise source in a communication link similar to electrical noise, but is a time domain noise variable affecting many different parts of the sampling process. Presented in this dissertation, the clock jitter effect on sampling is modeled for communication systems with the degree of accuracy needed for modern high speed data communication. The models developed and presented here have been used to develop the clocking specifications and silicon budgets for industry standards such as PCI Express, USB3.0, GDDR5 Memory, and HBM Memory interfaces.

Not available / text

Not available / text

No description available.

No description available.

No description available.

No description available.