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A sequence of electrical tests was developed to provide a viable alternative to the performance of high magnification visual inspection for high reliability integrated circuits in a large volume production environment. The primary approach was based on: close monitoring of the Substrate-N epi I-V characteristics, voltage overstress exposure and subsequent verification of the devices' low level leakage and thermal response. This method was implemented and evaluated for the specific case of a 16K Bipolar Schottky PROM. Reliability tests indicated that devices processed using the proposed alternate screen sequence achieved failure rates as low as those obtained using high magnification visual inspection.

The era of VLSI design necessitates the development of advanced Computer Aided Design tools. The main objective of this research was to introduce an intelligent automatic Sequential Circuit Test System, SCIRTSS, driven by A Hardware Programming Language, AHPL. SCIRTSS can handle the test vector generation process for VLSI circuits in an early state of the design loop, even before the generation of the final technology dependent network logic list. The driving force of the test generation process is the intelligent search program. The search program, supported by a set of heuristics and an accurate function level simulator, generates the test sequence to propagate the single fault effect to a primary output of the circuit. The test sequence generated is a concatenation of the sequences generated by the repeated searches on the state-space of the design. These sequences are verified by a parallel fault simulator. Design for testability techniques could be used to improve the test sequence generated. This system is user friendly and protable. Several circuits were tested under SCIRTSS, the results of some of them were introduced in this paper.

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by Chan, Ray. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1994. / Includes bibliographical references (leaves [93-96]). / ACKNOWLEDGMENT / ABSTRACT / FIGURE CAPTIONS / TABLE CAPTIONS / INTRODUCTION / Chapter I. --- PRINCIPLES OF SEM / Chapter 1.1 --- STRUCTURE OF SEM --- p.1-1 / Chapter 1.2 --- IMAGE FORMATION --- p.1-6 / Chapter 1.2.1 --- Electron Beam-Specimen Interaction --- p.1-6 / Chapter 1.2.1.1 --- Electron scattering in solid specimen --- p.1-7 / Chapter 1.2.1.2 --- Electron range and spatial distribution --- p.1-7 / Chapter 1.2.1.3 --- Back scattered electrons(BE) --- p.1-8 / Chapter 1.2.1.4 --- Secondary electron(SE) --- p.1-9 / Chapter 1.2.1.5 --- Other signal types --- p.1-13 / Chapter 1.2.2 --- Types of Image Contrast --- p.1-14 / Chapter 1.3 --- DISTORTION AND NOISE --- p.1-17 / Chapter 1.3.1 --- Lens Aberration --- p.1-17 / Chapter 1.3.1.1 --- Spherical aberration --- p.1-17 / Chapter 1.3.1.2 --- Chromatic aberration --- p.1-18 / Chapter 1.3.1.3 --- Diffraction effect --- p.1-19 / Chapter 1.3.1.4 --- Axial astigmatism --- p.1-20 / Chapter 1.3.1.5 --- Spatial resolution calculation --- p.1-21 / Chapter 1.3.2 --- Image Defects --- p.1-22 / Chapter 1.3.2.1 --- Projection distortion --- p.1-22 / Chapter 1.3.2.2 --- Specimen tilting --- p.1-22 / Chapter 1.3.2.3 --- Moire effects --- p.1-22 / Chapter 1.3.3 --- Noise in SEM --- p.1-23 / Chapter II. --- SEM FOR IC TESTING / Chapter 2.1 --- QUANTITATIVE ANALYSIS OF VOLTAGE MEASUREMENT --- p.2-1 / Chapter 2.1.1 --- Energy Analysis of SEs --- p.2-1 / Chapter 2.1.2 --- Suppression of Local Fields --- p.2-2 / Chapter 2.1.3 --- "Elimination of Topography, Material Contrast and Work Function Variation" --- p.2-2 / Chapter 2.2 --- VOLTAGE RESOLUTION --- p.2-3 / Chapter 2.3 --- TIME RESOLUTION --- p.2-4 / Chapter 2.3.1 --- SE Generation Time --- p.2-4 / Chapter 2.3.2 --- SE Flight Time --- p.2-4 / Chapter 2.3.3 --- Required Voltage Resolution --- p.2-5 / Chapter 2.3.4 --- Electron Beam Pulse Width --- p.2-5 / Chapter 2.4 --- SPATIAL RESOLUTION --- p.2-5 / Chapter 2.5 --- CAPACITIVE COUPLING VOLTAGE CONTRAST --- p.2-6 / Chapter III. --- SEM TESTING TECHNIQUES / Chapter 3.1 --- CONVENTIONAL TESTING METHODS SYNOPSIS --- p.3-1 / Chapter 3.2 --- TESTING TECHNIQUES FOR SEM --- p.3-2 / Chapter 3.2.1 --- Static Mode --- p.3-2 / Chapter 3.2.2 --- Frequency Matching Mode --- p.3-3 / Chapter 3.2.2.1 --- Voltage coding --- p.3-4 / Chapter 3.2.2.2 --- Stroboscopy --- p.3-4 / Chapter 3.2.2.3 --- Waveform measurement --- p.3-6 / Chapter 3.2.2.4 --- Logic state mapping --- p.3-6 / Chapter 3.2.2.5 --- Frequency tracing --- p.3-7 / Chapter 3.2.2.6 --- Frequency mapping --- p.3-8 / Chapter 3.2.2.7 --- Logic state tracing --- p.3-9 / Chapter IV. --- CONVERT AMRAY 1830 INTO E-BEAM TESTER / Chapter 4.1 --- DESIGN CONSIDERATION --- p.4-1 / Chapter 4.1.1 --- Application Consideration --- p.4-1 / Chapter 4.1.2 --- Limitation of the AMRAY 1830 --- p.4-1 / Chapter 4.1.2.1 --- Detection system --- p.4-2 / Chapter 4.1.2.2 --- Scanning driver --- p.4-3 / Chapter 4.1.2.3 --- Beam blanker --- p.4-4 / Chapter 4.1.2.4 --- NibbleNet interface --- p.4-5 / Chapter 4.2 --- HARDWARE ARCHITECTURE --- p.4-6 / Chapter 4.2.1 --- SEM Circuit Varied --- p.4-7 / Chapter 4.2.1.1 --- Adding scanning relays --- p.4-7 / Chapter 4.2.1.2 --- Voltage clippers --- p.4-7 / Chapter 4.2.1.3 --- External scan interface in SEM --- p.4-9 / Chapter 4.2.2 --- PC Interface --- p.4-9 / Chapter 4.2.3 --- Driver Box --- p.4-10 / Chapter 4.2.3.1 --- Data preprocess unit --- p.4-10 / Chapter 4.2.3.2 --- Scanning preprocess unit --- p.4-12 / Chapter 4.2.3.3 --- Control unit --- p.4-12 / Chapter 4.2.4 --- Scanning Generation and Data Acquisition --- p.4-13 / Chapter 4.3 --- SOFTWARE DEVELOPED --- p.4-13 / Chapter 4.3.1 --- Function Library --- p.4-13 / Chapter 4.3.2 --- Integrated Environment --- p.4-14 / Chapter V. --- SYSTEM PERFORMANCE / Chapter 5.1 --- CHARACTERISTICS OF THE SCANNING DRIVERS --- p.5-1 / Chapter 5.1.1 --- Driver Output Changes with Acceleration Voltage --- p.5-2 / Chapter 5.1.2 --- Driver Output Changes with magnification --- p.5-3 / Chapter 5.1.3 --- Frequency Response --- p.5-4 / Chapter 5.1.4 --- Image Distortion --- p.5-7 / Chapter 5.2 --- INTEGRATED STUDY ENVIRONMENT --- p.5-9 / Chapter 5.2.1 --- Setting Status --- p.5-9 / Chapter 5.2.2 --- Image Scanning & Image Saving --- p.5-12 / Chapter 5.2.3 --- Static Probing --- p.5-15 / Chapter 5.2.4 --- Point Probing --- p.5-19 / Chapter 5.2.5 --- Frequency Matching --- p.5-20 / Chapter V. --- SUMMARY --- p.6-1 / REFERENCE / APPENDIX: / Chapter A. --- PROGRAM LISTING / Chapter B. --- CIRCUIT SCHEMATICS

The feasibility of developing test circuits to perform in-circuit testing of analog circuits is investigated in this thesis. A modular approach to analog testing has been adopted. Accordingly, the testing of an operational amplifier, which is a basic building block in analog circuits, is addressed. One convenient technique for measuring the frequency response of an op-amp requires a unity gain buffer to be inserted into its feedback loop. This buffer has to be simple in construction, small and accurate. Two buffer circuits that satisfy these requirements are described in this thesis. Enhanced slewing techniques are devised to achieve increased levels of performance. The buffers were integrated with an op-amp into a test chip. Digital logic is used to provide controllability and accessibility to each of the buffers and the op-amp so that they can characterized separately. The performance of the enhanced slewing buffers was verified with measurements performed on the test chip. The performance of the buffers conformed well with the simulated values. The buffers exhibited excellent settling times even while driving large capacitive loads. Their output swing and distortion performance were good for inputs as large as 2 V peak-to-peak values. / Graduation date: 1994

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