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Isotropic and anisotropic etching have been used in silicon processing for the past few decades. However, optimization and adaptation of anisotropic etching to standard I.C. fabrication is a more recent technology. This paper describes new methods for process and material optimization in Orientation and Concentration dependent etching of the (1 0 0) plane in silicon. Furthermore, methods of oxide and nitride pinhole detection in (1 0 0) planes in silicon are presented. New mask alignment techniques to obtain an accurate etch front termination in silicon are also shown.

Jiang, Li. / Thesis (Ph.D.)--Chinese University of Hong Kong, 2013. / Includes bibliographical references (leaves 149-155). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstracts also in Chinese.

by Hu Hai. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2006. / Includes bibliographical references. / Abstracts in English and Chinese. / Author's Declaration --- p.ii / Abstract --- p.iii / Acknowledgements --- p.vi / Table of Contents --- p.viii / List of Figures --- p.xi / List of Tables --- p.xiv / Chapter Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Background --- p.1 / Chapter 1.2 --- Overview of This Work --- p.2 / Chapter 1.3 --- Original Contributions in the Thesis --- p.3 / Chapter 1.4 --- Thesis Organization --- p.4 / Chapter Chapter 2 --- PEEC Modeling Background --- p.5 / Chapter 2.1 --- Introduction --- p.5 / Chapter 2.2 --- PEEC Principles --- p.6 / Chapter 2.3 --- Meshing Scheme --- p.10 / Chapter 2.4 --- Formulae for Calculating the Partial Elements --- p.12 / Chapter 2.4.1 --- Partial Inductance --- p.12 / Chapter 2.4.2 --- Partial Capacitance --- p.14 / Chapter 2.5 --- PEEC Application Example --- p.15 / Chapter 2.6 --- Summary --- p.17 / References --- p.18 / Chapter Chapter 3 --- Mathematical Model Order Reduction --- p.20 / Chapter 3.1 --- Introduction --- p.20 / Chapter 3.2 --- Modified Nodal Analysis --- p.21 / Chapter 3.2.1 --- Standard Nodal Analysis Method Review --- p.22 / Chapter 3.2.2 --- General Theory of Modified Nodal Analysis --- p.23 / Chapter 3.2.3 --- Calculate the System Poles Using MNA --- p.27 / Chapter 3.2.4 --- Examples and Comparisons --- p.28 / Chapter 3.3 --- Krylov Subspace MOR Method --- p.30 / Chapter 3.4 --- Examples of Krylov Subspace MOR --- p.32 / Chapter 3.5 --- Summary --- p.34 / References --- p.35 / Chapter Chapter 4 --- Physical Model Order Reduction --- p.38 / Chapter 4.1 --- Introduction --- p.38 / Chapter 4.2 --- Gaussian Elimination Method --- p.39 / Chapter 4.3 --- A Lossy PEEC Circuit Model --- p.44 / Chapter 4.3.1 --- Loss with Capacitance --- p.44 / Chapter 4.3.2 --- Loss with Inductance --- p.46 / Chapter 4.4 --- Conversion of Mutual Inductive Couplings --- p.47 / Chapter 4.5 --- Model Order Reduction Schemes --- p.50 / Chapter 4.5.1 --- Taylor Expansion Based MOR Scheme (Type I) --- p.51 / Chapter 4.5.2 --- Derived Complex-valued MOR Scheme (Type II) --- p.65 / Chapter 4.6 --- Summary --- p.88 / References --- p.88 / Chapter Chapter 5 --- Concluding Remarks --- p.92 / Chapter 5.1 --- Conclusion --- p.92 / Chapter 5.2 --- Future Improvement --- p.93 / Author's Publication --- p.95

Ip, Wei Chi. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2011. / Includes bibliographical references (leaves 92-94). / Abstracts in English and Chinese. / Abstract --- p.i / 摘要 --- p.ii / Acknowledgement --- p.iii / Table of Content --- p.iv / Lists of Figures --- p.vii / Lists of Tables --- p.xii / Chapter Chapter 1: --- Introduction --- p.1 / Chapter 1.1 --- Research Motivation and Obj ective --- p.1 / Chapter 1.2 --- Original Contribution --- p.2 / Chapter 1.3 --- Overview of the Thesis Organization --- p.3 / Chapter 1.4 --- "Research Approach, Assumptions and Limitations" --- p.4 / Chapter Chapter 2: --- Power Divider Design Fundamentals --- p.5 / Chapter 2.1 --- Power Divider Basics --- p.5 / Chapter 2.2 --- Wilkinson Power Divider --- p.6 / Chapter 2.3 --- Power Divider with Unequal Power Division --- p.8 / Chapter 2.4 --- Multi-way Power Divider --- p.9 / Chapter 2.4.1 --- Wilkinson N-way Hybrid --- p.10 / Chapter 2.4.2 --- Radial Hybrid --- p.11 / Chapter 2.4.3 --- Fork Hybrid --- p.12 / Chapter 2.4.4 --- Multi-layer Approach --- p.IS / Chapter 2.4.5 --- Power Recombination Concept --- p.15 / Chapter 2.4.6 --- Multi-coupled-line Approach --- p.18 / Chapter Chapter 3: --- Conventional Power Divider Designs with Harmonic Suppression --- p.20 / Chapter 3.1 --- Resonating-stubs Topology --- p.20 / Chapter 3.2 --- Asymmetric Defected Ground Structure (DGS) --- p.26 / Chapter 3.3 --- Anti-Coupled Line Structure --- p.30 / Chapter 3.4 --- Microstrip Electromagnetic Bandgap (EBG) Based Topology --- p.32 / Chapter 3.5 --- Embedded Resonators Topology --- p.37 / Chapter 3.6 --- Extended Line Approach --- p.39 / Chapter Chapter 4: --- New 2-way Power Divider Design with Spurious Suppression and Impedance Transformation --- p.41 / Chapter 4.1 --- Proposed Topology --- p.41 / Chapter 4.2 --- Design and Analysis --- p.42 / Chapter 4.3 --- Simulation Study --- p.45 / Chapter 4.4 --- Experimental Verification --- p.50 / Chapter 4.5 --- Summary --- p.57 / Chapter Chapter 5: --- New 2-way Power Divider Design with Extended Spurious Suppression --- p.58 / Chapter 5.1 --- Proposed Topology --- p.58 / Chapter 5.2 --- Design and Analysis --- p.59 / Chapter 5.3 --- Simulation Study --- p.64 / Chapter 5.3 --- Experimental Verification --- p.68 / Chapter 5.4 --- Summary --- p.71 / Chapter Chapter 6: --- New 2-way Unequal Power Divider Design with Dual-harmonic Rejection --- p.72 / Chapter 6.1 --- Proposed Topology --- p.72 / Chapter 6.2 --- Design and Analysis --- p.73 / Chapter 6.3 --- Simulation Study --- p.76 / Chapter 6.4 --- Experimental Verification --- p.77 / Chapter 6.4 --- Summary --- p.80 / Chapter Chapter 7: --- New 3-way Power Divider Design with Multi-harmonic Rejection..… --- p.81 / Chapter 7.1 --- Proposed Topology --- p.81 / Chapter 7.2 --- Design and Analysis --- p.82 / Chapter 7.3 --- Simulation Study --- p.85 / Chapter 7.4 --- Experimental Verification --- p.87 / Chapter 7.4 --- Summary --- p.90 / Chapter Chapter 8: --- Conclusion --- p.91 / References --- p.92 / Author's Publications and Awards --- p.95 / Chapter Appendix 1: --- ABCD Parameters of Some Useful Two-port Circuits --- p.96 / Chapter Appendix 2: --- More Designs of Proposed Configuration in Chapter 5 --- p.97 / Chapter A2.1 --- Miniaturized version of Example 1 --- p.97 / Chapter A2.2 --- Design with improved stop-band response --- p.101 / Chapter A2.3 --- Design of prototype with 2 GHz operating frequency --- p.104 / Chapter Appendix 3: --- Brief Summary of Power Dividers with Harmonic Suppression --- p.108

To reduce chip-scale topography variation, dummy fill is commonly used to improve the layout density uniformity. Previous works either sought the most uniform density distribution or sought to minimize the inserted dummy fills while satisfying certain density uniformity constraint. However, due to more stringent manufacturing challenges, more criteria, like line deviation and outlier, emerge at newer technology nodes. / This work presents a joint optimization scheme to consider variation, total fill, line deviation, outlier, overlap and running time simultaneously. More specifically, we first partition the rectilinear fillable regions into rectangles for later processing. Inspired by the work–PTR (Polygon-To-Rectangle) in [3], we implement I-PTR (Improved PTR) and another new decomposition algorithm called L-PTR (Lowest overlapping edge PTR) to divide the fillable regions into rectangles according to the window boundaries on one hand and to get more large resulting rectangles on the other hand. After decomposition, we insert dummy fills into the fillable rectangular regions optimizing the fill metrics simultaneously. We propose three approaches–Fast Median approach, LP approach and Iterative approach. Among the three fill insertion algorithms, Fast Median is proven to be the best. Therefore we compare Fast Median with the top three contestants in the ICCAD Contest 2014 on the industrial benchmarks released by the contest organizer. Experiments show that Fast Median is 25× faster than the fastest one among the top three teams, and its quality score (0.70) outperforms the top three teams of which the scores are 0.63, 0.61 and 0.61 respectively. / 為了降低芯片的密度差異，冗餘的金屬填充物通常會被用來提高布線板的密度均勻性。過去的研究工作要麼一味以最大化均勻性为目标，要麼在滿足一定的密度差異的基礎上以加入佈線板的金屬填充物的總量最少为目标。然而，由於更加嚴格的工業製造挑戰，很多新的目標越來越舉足輕重，比如列密度差和異常值。 / 本文提出了同時考慮總差異、填充物總量、列密度差、異常值、重疊和運行時間的優化方法。具體來說，首先我們將表示可填充區域的直角多邊形分解成矩形，方便後續的處理。受到相關工作——PTR[3]的啟發，我們實現了I-PTR和另外一種新的分解算法L-PTR來分解可填充區域，一方面，我們根據窗口邊界來分解，另一方面我們盡量分解得到更多大面積矩形。分解之後，我們將金屬填充物加入到可填充區域，同時優化各個目標函數。我們提出了三種優化方法——快速中值法，LP法和迭代法。在這三種方法當中，快速中值法被證明是最好的。所以我们将快速中值法與ICCAD 2014年競賽的前三名算法分別運用在比賽發佈的測試集上，進行對比。實驗數據表明，我們的快速中值法比前三名最快的還要快25倍。並且，我們的總得分（0.70）要優於前三名的得分（分别是0.63、0.61和0.61）。 / Liu, Chuangwen. / Thesis M.Phil. Chinese University of Hong Kong 2015. / Includes bibliographical references (leaves 59-62). / Abstracts also in Chinese. / Title from PDF title page (viewed on 12, October, 2016). / Detailed summary in vernacular field only. / Detailed summary in vernacular field only.

published_or_final_version / Electrical and Electronic Engineering / Doctoral / Doctor of Philosophy

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