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The primary objective of the work described in this thesis was to study the influence of undoped LEC GaAs substrate material from various suppliers on the performance of ion implanted and annealed active layers. Optical transient current spectroscopy (OTCS) was investigated as a qualification test for GaAs substrates. Deep level spectra of the substrates before ion implantation were obtained. It was found that while the OTCS spectra of high pressure grown GaAs from two suppliers were similar, that of the low pressure material showed different relative concentration of traps. The use of OTCS was further extended to study trap concentration as a function of surface treatment. It was found that the use of chemical etchants reduces the concentration of some levels, possibly those located on the surface as opposed to bulk traps. Surface damage was found to enhance the negative peak in the OTCS spectrum. The deep levels spectra were found to be affected by the geometry of the device and the type of electrode material. Channel current deep level transient spectroscopy (DLTS) was used to study both process- and substrate-induced deep levels in ion implanted MESFET channels. The spectra of process-induced traps were found to be different according to the encapsulant used. Silicon dioxide (both RF sputtered and plasma enhanced chemically vapor deposited (PECVD)) was found to induce a variety of process related defects. This is believed to be because silicon dioxide is permeable to gallium and hence does not preserve the stoichiometry of ion implanted GaAs during high temperature anneals. Deep level spectra of MESFETs annealed using silicon nitride, on the other hand, were found to contain single traps related to the defects in the starting material. For implants through silicon nitride, a high concentration of the main electron trap EL2 was found, whereas implants directly into the surface resulted in the level EL12. Comparison of the characteristics of the variety of LEC undoped GaAs material show that they differed widely and had inhomogeneous properties. For example, compared to the high pressure grown GaAs, the Litton’s low pressure substrate had lower activation, mobility, drain current and threshold voltage, good confinement of the scatter in the same characteristics, low concentration of deep levels, and the least backgating effect which makes it promising for IC fabrication. Comparison of the high pressure grown material from two suppliers showed that Cominco's recent material had good mobility, activation, relatively high scatter of threshold voltage, high concentration of deep levels, and was affected by backgating. In comparison, Sumitomo's material showed thermal instability, less scatter of threshold voltage, less mobility and deep level concentrations, and similar backgating characteristics. Substrate grown three years earlier showed higher diffusion of dopant, different deep levels, and better backgating characteristics. Finally, a substrate which had failed the qualification test by a device manufacturer showed minimal diffusion tails and threshold voltage scatter, the highest concentration of deep levels, and substantial backgating. / Applied Science, Faculty of / Electrical and Computer Engineering, Department of / Graduate

As datapath chips such as microprocessors and digital signal processors become more complex, efficient CAD tools that preserve the regularity of datapath designs and result in small layout area are required. The standard-cell placement techniques ignore the regularity of datapath designs and hence give inefficient layouts. This has necessitated the development of new techniques for datapath module placement. We developed a layout synthesis tool DataPathLAYOUT, for the bit-slice datapath logic designed using standard-cell libraries. We developed fast and area efficient heuristics for placing the cells in a bit-slice such that the regularity of datapath circuits is preserved and the number of channels in which a control signal is routed is minimized. The placement heuristics proposed here are general and also applicable to regular logic like systolic arrays. In addition, we propose a novel window- based heuristic, applicable to datapath and non-datapath circuits, for global routing of multi-terminal nets. We compared the area and run-time efficiency of the DPLAYOUT with an existing standard-cell placement and routing tool. We achieved 98-99% improvement in placement time, 28-33% improvement in area and 8-80% in total time. We conducted some experiments and demonstrated that for standard-cell based datapath designs, bit-slice-based layout generation approach is superior to non-bit-slice-based layout generation approach both in terms of area and run-time. Finally, by providing interface to Verilog hardware description language, we developed a general tool which can be easily integrated with any highlevel synthesis system. This tool is critical in any Datapath Silicon Compiler, to generate mask geometries from the behavioral level input specifications written in a hardware description language.

Ultra-low-voltage (ULV) operation where the supply voltage of the digital computing hardware is scaled down to the level near or below transistor threshold voltage (e.g. 300-500mV) is a key technique to achieve high computing energy efficiency. It has enabled many new exciting applications in the field of Internet of Things (IoT) devices and energy-constrained applications such as medical implants, environment sensors, and micro-robots. Ultra-low-voltage (ULV) operation is also commonly used with the emerging architectures that are often non Von-Neumann style to empower energy-efficient cognitive computing. One the biggest challenge in realizing ULV design is the large circuit delay variability. To guarantee functionality in the worst-case process, voltage, and temperature (PVT) condition, the traditional safety margin approach requires operating at a slower clock frequency or higher supply voltage which significantly limits the achievable energy efficiency of the hardware. To fully claim the energy efficiency of ULV, the large circuit delay variation needs to be adaptively handled. However, the existing adaptive techniques that are optimized for nominal supply voltage operation and traditional Von-Neumann architectures become inefficient for ULV designs and emerging architectures. This thesis presents adaptive techniques based on timing error detection and correction (EDAC) that are more suitable for the energy-constrained ULV designs and the emerging architectures. The proposed techniques are demonstrated in three test chips: (1) R-Processor: A 0.4V resilient processor with a voltage-scalable and low-overhead in-situ EDAC technique. It achieves 38% energy efficiency improvement or 2.3X throughput improvement as compared to the traditional safety margin approach. (2) A 450mV timing-margin-free waveform sorter for brain computer interface (BCI) microsystem. It achieves 49.3% higher energy efficiency and 35.6% higher throughput than the traditional safety margin approach. (3) Ultra-low-power and robust power-management system which consists of a microprocessor employing ULV EDAC, 63-ratio integrated switched-capacitor DC-DC converter, and a fully-digital error based regulation controller. In this thesis, we also explore circuits for emerging techniques. The first is temperature sensors for dynamic-thermal-management (DTM). The modern high-performance microprocessors suffer from ever-increasing power densities which has led to reliability concerns and increased cooling costs from excessive heat. In order to monitor and manage the thermal behavior, DTM techniques embed multiple temperature sensors and use its information. The size, accuracy, and voltage-scalability of the sensor are critical for the performance of DTM. Therefore, we propose a temperature sensor that directly senses transistor threshold voltage and the test chip demonstrates 9X smaller area, 3X higher accuracy, and 200mV lower voltage scalability (down to 400mV) than the previous state-of-art. Another area of exploration is interconnect design for ultra-dynamic-voltage-scaling (UDVS) systems. UDVS has been proposed for applications that require both high performance and high energy efficiency. UDVS can provide peak performance with nominal supply voltage when work load is high. When work load is moderate or low, UDVS systems can switch to ULV operation for higher energy efficiency. One of the critical challenges for developing UDVS systems is the inflexibility in various circuit fabrics that are often optimized for a single supply voltage. One critical example is conventional repeater based long interconnects which suffers from non-optimal performance and energy efficiency in UDVS systems. Therefore, in this thesis, we propose a reconfigurable interconnect design based on regenerators and demonstrate near optimal performance and energy efficiency across the supply voltage of 0.3V and 1V.

Reactive ion etching has been used to obtain anisotropic silicon trenches with small sidewall angles. This work demonstrates that the sidewall angle can be controlled by the wafer temperature and there exists an Arrhenius-type relationship among isotropic polymer deposition rate, thickness of polymer, and sidewall angle.

Two computer-aided design methods are described in this dissertation for the design of Thermionic Integrated Circuits (TIC). Such circuits combine vacuum tube techniques with modern integrated circuit techniques to produce microminiature vacuum tube circuits, with possibly hundreds of vacuum triodes on a single substrate. The first method described in the line charge approximation technique in which the TIC devices are modelled as collections of line charges. A TIC is produced by evaporating metal electrodes on one or two sapphire substrates. The entire structure is heated to about 850°C so that electrons are emitted from the cathode electrodes to travel to the plate electrodes as in a conventional vacuum triode. The line charge approximation method is easy to implement and provides a simple means of satisfying the sapphire dielectric boundary conditions of the TIC basic problems, which are electrostatics problems since space charge effects are neglected. The method requires only a single matrix inversion and is a finite element Green's function approach. The method uses no iteration as in previous TIC analysis methods. Later as the development of TIC devices proceeded further it was found that conducting shields had to be placed over the unused sapphire surface so that the basic problem became a metal box problem. For this case a second method was developed called the step and ramp function method in which each electrode is modelled by a step function, which is the electric field solution for a potential step on a zero potential boundary. A superposition of these step functions models the TIC electrodes. The method provides direct calculation of the electric fields from equations and requires no iteration or matrix inversion. The potential variation between electrodes is modelled by linear potential functions called ramps. A superposition of steps and ramps completely specifies a TIC structure. The method does not solve for the case of electrodes which are elevated above substrates. For this case a modified line charge method was developed but not implemented.

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published_or_final_version / abstract / Electrical and Electronic Engineering / Master / Master of Philosophy