The very low photon backgrounds to be achieved by future cryogenic astronomical telescopes present the ultimate challenge to the sensitivity of infrared detectors and associated readout electronics. Cooled silicon JFETs, operated around 70 K in transimpedance amplifiers, have shown excellent performance and stability. However, due to Johnson noise in the feedback resistor, the read noise in one second achieved by such amplifiers is about 500 electrons per second. A drastic improvement in sensitivity was demonstrated using a simple form of integrating JFET amplifiers. Therefore, the excellent performance obtained with cooled silicon JFETs has led to the investigation of their properties in the temperature range 33-77 K to explore their full potential and improve the performance of the integrating amplifier. The freezeout effect in silicon JFETs has been characterized both experimentally and theoretically using a simple analytical simulation program. The effect of variation in device parameters on the freezeout characteristic has been studied, and test results showed that an effective channel mobility must be used instead of a bulk mobility in order to simulate accurately the device current and transconductance freezeout at low temperatures. Many types of commercially available JFETs have been characterized below 77 K and measurements revealed that a balanced source follower or a common-source amplifier with active load can operate well down to 38 Kelvin with extremely low power dissipation. The open gate equivalent input noise voltage was found to be optimum below 77 K, due to a decrease in the gate leakage current, in agreement with theoretical prediction. Based on the superior performance of the balanced source follower with active load, a single channel hybrid integrating JFET amplifier with a JFET reset and a compensation capacitor was developed for operation in the temperature range 40-77 K. Read noise as low as 10 electrons in 128 seconds integration was achieved when the integrator was operated at an optimum temperature of about 55 K. Using a similar design, a 16-channel monolithic integrating amplifier array was designed and built. Preliminary test results at 77 K showed noise performance comparable to the single channel hybrid integrator.

No description available.

No description available.

The LAMBDA-DIODE was invented in integrated-circuit form in 1974. There was a proposal about this device's application in memory circuits at that time. This thesis is to evaluate the circuit performance of the COMPLEMENTARY JFET LAMBDA-DIODE SRAM. It investigates the speed, power consumption and chip area of this circuit compared with the JFET CROSS COUPLED SRAM by using SPICE and breadboard simulation techniques. The results show positive signs of the Λ-DIODE's feasibility for use in VLSI static memory circuits from the chip area aspect if the parasitic capacitance of the JFET device could be minimized to reduce the power delay product.

CGRAs (coarse grained reconfigurable array architectures) try to fill the gap between FPGAs and ASICs. Over three decades, the research towards CGRA design has produced number of architectures. Each of these designs lie at different points on a line drawn between FPGAs and ASICs, depending on the tradeoffs and design choices made during the design of architectures. Thus, design space exploration (DSE) takes a very important role in the circuit design process. In this work I propose the design space exploration of CGRAs can be done quickly and efficiently through crowd-sourcing and a game driven approach based on an interactive mapping game UNTANGLED and a design environment called SmartBricks. Both UNTANGLED and SmartBricks have been developed by our research team at Reconfigurable Computing Lab, UNT. I present the results of design space exploration of domain-specific reconfigurable architectures and compare the results comparing stripe vs mesh style, heterogeneous vs homogeneous. I also compare the results obtained from different interconnection topologies in mesh. These results show that this approach offers quick DSE for designers and also provides low power architectures for a suite of benchmarks. All results were obtained using standard cell ASICs with 90 nm process.

Tang Siu Kei. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2004. / Includes bibliographical references (leaves 107-111). / Abstracts in English and Chinese. / Acknowledgements --- p.ii / Abstract --- p.iii / List of Figures --- p.xi / List of Tables --- p.xvi / Chapter Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Overview of Electrostatic Discharge --- p.1 / Chapter 1.1.1 --- Classification of Electrostatic Discharge Models --- p.1 / Chapter 1.2 --- Electrostatic Discharge in CMOS RF Circuits --- p.4 / Chapter 1.3 --- Research Goal and Contribution --- p.6 / Chapter 1.4 --- Thesis Outline --- p.6 / Chapter Chapter 2 --- Performance Parameters of Amplifier --- p.8 / Chapter 2.1 --- Amplifier Gain --- p.8 / Chapter 2.2 --- Noise Factor --- p.9 / Chapter 2.3 --- Linearity --- p.11 / Chapter 2.3.1 --- 1-dB Compression Point --- p.13 / Chapter 2.3.2 --- Third-Order Intercept Point --- p.14 / Chapter 2.4 --- Return Loss --- p.16 / Chapter 2.5 --- Power Consumption --- p.18 / Chapter 2.6 --- HBM ESD Withstand Voltage --- p.19 / Chapter Chapter 3 --- ESD Protection Methodology for Low Noise Amplifier --- p.21 / Chapter 3.1 --- Dual-Diode Circuitry --- p.22 / Chapter 3.1.1 --- Working Principle --- p.22 / Chapter 3.1.2 --- Drawbacks --- p.24 / Chapter 3.2 --- Shunt-Inductor Method --- p.25 / Chapter 3.2.1 --- Working Principle --- p.25 / Chapter 3.2.2 --- Drawbacks --- p.27 / Chapter 3.3 --- Common-Gate Input Stage Method --- p.28 / Chapter 3.3.1 --- Built-in ESD Protecting Mechanism --- p.29 / Chapter 3.3.2 --- Competitiveness --- p.31 / Chapter Chapter 4 --- Design Theory of Low Noise Amplifier --- p.32 / Chapter 4.1 --- Small-Signal Modeling --- p.33 / Chapter 4.2 --- Method of Input Termination --- p.33 / Chapter 4.2.1 --- Resistive Termination --- p.34 / Chapter 4.2.2 --- Shunt-Series Feedback --- p.34 / Chapter 4.2.3 --- l/gm Termination --- p.35 / Chapter 4.2.4 --- Inductive Source Degeneration --- p.36 / Chapter 4.3 --- Method of Gain Enhancement --- p.38 / Chapter 4.3.1 --- Tuned Amplifier --- p.38 / Chapter 4.3.2 --- Multistage Amplifier --- p.40 / Chapter 4.4 --- Improvement of Reverse Isolation --- p.41 / Chapter 4.4.1 --- Common-Gate Amplifier --- p.41 / Chapter 4.4.2 --- Cascoded Amplifier --- p.42 / Chapter Chapter 5 --- Noise Analysis of Low Noise Amplifier --- p.44 / Chapter 5.1 --- Noise Sources of MOS Transistor --- p.44 / Chapter 5.2 --- Noise Calculation using Noisy Two-Port Network --- p.46 / Chapter 5.3 --- Noise Calculation using Small-Signal Model --- p.49 / Chapter 5.3.1 --- Low Noise Amplifier with Inductive Source Degeneration --- p.49 / Chapter 5.3.2 --- Common-Gate Low Noise Amplifier --- p.52 / Chapter Chapter 6 --- Design of an ESD-protected CMOS Low Noise Amplifier --- p.54 / Chapter 6.1 --- Design of DC Biasing Circuitry --- p.55 / Chapter 6.2 --- Design of Two-Stage Architecture --- p.57 / Chapter 8.3.1 --- Design of Common-Gate Input Stage --- p.57 / Chapter 8.3.2 --- Design of Second-Stage Amplifier --- p.59 / Chapter 6.3 --- Stability Consideration --- p.61 / Chapter 6.4 --- Design of Matching Networks --- p.62 / Chapter 6.4.1 --- Design of Inter-Stage Matching Network --- p.64 / Chapter 6.4.2 --- Design of Input and Output Matching Networks --- p.67 / Chapter Chapter 7 --- Layout Considerations --- p.70 / Chapter 7.1 --- MOS Transistor --- p.70 / Chapter 7.2 --- Capacitor --- p.72 / Chapter 7.3 --- Spiral Inductor --- p.74 / Chapter 7.4 --- Layout of the Proposed Low Noise Amplifier --- p.76 / Chapter 7.5 --- Layout of the Common-Source Low Noise Amplifier --- p.79 / Chapter 7.6 --- Comparison between Schematic and Post-Layout Simulation Results --- p.81 / Chapter Chapter 8 --- Measurement Results --- p.82 / Chapter 8.1 --- Experimental Setup --- p.82 / Chapter 8.1.1 --- Testing Circuit Board --- p.83 / Chapter 8.1.2 --- Experimental Setup for s-parameter --- p.84 / Chapter 8.1.3 --- Experimental Setup for Noise Figure --- p.84 / Chapter 8.1.4 --- Experimental Setup for 1-dB Compression Point --- p.85 / Chapter 8.1.5 --- Experimental Setup for Third-Order Intercept Point --- p.86 / Chapter 8.1.6 --- Setup for HBM ESD Test --- p.87 / Chapter 8.2 --- Measurement Results of the Proposed Low Noise Amplifier --- p.89 / Chapter 8.2.1 --- S-parameter Measurement --- p.90 / Chapter 8.2.2 --- Noise Figure Measurement --- p.91 / Chapter 8.2.3 --- Measurement of 1-dB Compression Point --- p.92 / Chapter 8.2.4 --- Measurement of Third-Order Intercept Point --- p.93 / Chapter 8.2.5 --- HBM ESD Test --- p.94 / Chapter 8.2.6 --- Summary of Measurement Results --- p.95 / Chapter 8.3 --- Measurement Results of the Common-Source Low Noise Amplifier --- p.96 / Chapter 8.3.1 --- s-parameter Measurement --- p.97 / Chapter 8.3.2 --- Noise Figure Measurement --- p.98 / Chapter 8.3.3 --- Measurement of 1-dB Compression Point --- p.99 / Chapter 8.3.4 --- Measurement of Third-Order Intercept Point --- p.100 / Chapter 8.3.5 --- HBM ESD Test --- p.101 / Chapter 8.3.6 --- Summary of Measurement Results --- p.102 / Chapter 8.4 --- Performance Comparison between Different Low Noise Amplifier Designs --- p.103 / Chapter Chapter 9 --- Conclusion and Future Work --- p.105 / Chapter 9.1 --- Conclusion --- p.105 / Chapter 9.2 --- Future Work --- p.106 / References --- p.107 / Author's Publications --- p.112

Lo Wing Hang. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2005. / Includes bibliographical references (leaves 60-61). / Abstracts in English and Chinese. / Abstract --- p.i / Chapter 1 --- Introduction --- p.1 / Chapter 2 --- Preliminaries --- p.5 / Chapter 2.1 --- Backgrounds and Definitions --- p.5 / Chapter 2.1.1 --- Boolean Network --- p.5 / Chapter 2.1.2 --- Transitive Fanin and Fanout Cone --- p.6 / Chapter 2.1.3 --- Controlling and Sensitizing Values --- p.6 / Chapter 2.1.4 --- Stuck-at Faults and Test Generation --- p.6 / Chapter 2.1.5 --- Mandatory Assignments --- p.8 / Chapter 2.2 --- Review of ATPG-based Rewiring --- p.9 / Chapter 3 --- Improved Single-Pass Rewiring Scheme Using Inconsistent Assignments --- p.14 / Chapter 3.1 --- Introduction --- p.14 / Chapter 3.2 --- Overview of FIRE --- p.15 / Chapter 3.3 --- Alternative Wire Identification Method --- p.17 / Chapter 3.3.1 --- Identifying Candidate Wires --- p.17 / Chapter 3.3.2 --- Redundancy Test on Candidate Wire --- p.18 / Chapter 3.4 --- Redundancy Identification Using Inconsistent Assignments --- p.21 / Chapter 3.5 --- Experimental Results --- p.26 / Chapter 3.6 --- Conclusions --- p.28 / Chapter 4 --- Improving Circuit Partitioning With Rewiring Techniques --- p.29 / Chapter 4.1 --- Introduction --- p.29 / Chapter 4.2 --- Implementation of Rewiring Schemes --- p.31 / Chapter 4.3 --- Coupling Partitioning Algorithm With Rewiring Techniques --- p.33 / Chapter 4.4 --- Experimental Results --- p.37 / Chapter 4.5 --- Conclusions --- p.43 / Chapter 5 --- Circuit Logic Level Reduction by Rewiring for FPGA Mapping --- p.45 / Chapter 5.1 --- Introduction --- p.45 / Chapter 5.2 --- Overview of the Technology Mapping Problem --- p.47 / Chapter 5.2.1 --- Problem Formulation --- p.47 / Chapter 5.2.2 --- FlowMap Algorithm Outline --- p.49 / Chapter 5.3 --- Logic Level Reduction by Rewiring Transformations --- p.51 / Chapter 5.4 --- Experimental Results --- p.54 / Chapter 5.5 --- Conclusions --- p.57 / Chapter 6 --- Conclusions and Future Works --- p.58 / Bibliography --- p.60

The integration of high-performance analog and digital circuits leads to an increasing need of new tools compatible for both the digital and analog parts. Unfortunately, the low acceptance of CAD tools in the analog domain presents a serious bottleneck to the fast realization of mixed-signal systems. Due to a higher sensitivity of the electrical performance to layout details, analog designs are much more complicated than digital ones. Process and temperature variations can introduce severe mismatches in devices that are designed to behave identically. These undesirable effects can be alleviated by a symmetric layout. Matching and symmetry in placement and routing in analog circuits are thus of immense importance. / In this thesis, we will present an effective layout method for analog circuits. We consider symmetry constraint, common centroid constraint, device merging and device clustering during the placement step. Symmetric routing will then be performed. In order to have successful routing, we will perform analog-based routability-driven adjustment during the placement process, taking into account for analog circuits that wires are not preferred to be layout on top of active devices. All these concepts were put together in our tool. Experimental results show that we can generate quality analog layout within minutes of time that passes the design rule check, layout-schematic verification and the simulation results are comparable to those of manual design, while a manual design will take a designer a couple of days to generate. / Xiao, Linfu. / Thesis (Ph.D.)--Chinese University of Hong Kong, 2012. / Includes bibliographical references (leaves 146-154). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstract --- p.i / Acknowledgement --- p.ii / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Analog Layout Problem --- p.2 / Chapter 1.1.1 --- Analog Circuit Design Flow --- p.3 / Chapter 1.1.2 --- An Example: μA741 Operational Amplifier --- p.5 / Chapter 1.1.3 --- Analog Layout Problem --- p.6 / Chapter 1.2 --- Thesis Contribution and Organization --- p.8 / Chapter 2 --- Background --- p.11 / Chapter 2.1 --- Analog Layout Basics --- p.11 / Chapter 2.1.1 --- Parasitic Effects --- p.12 / Chapter 2.1.2 --- Signal Coupling Effects --- p.13 / Chapter 2.1.3 --- Process Variation Effects --- p.15 / Chapter 2.2 --- Previous Analog Layout Automation Tools --- p.18 / Chapter 2.3 --- Previous Analog Layout Automation Approaches --- p.22 / Chapter 2.3.1 --- Device Generation --- p.23 / Chapter 2.3.2 --- Analog Placement --- p.25 / Chapter 2.3.3 --- Analog Routing --- p.37 / Chapter 3 --- System Overview --- p.45 / Chapter 3.1 --- System Flow Map --- p.45 / Chapter 3.1.1 --- Device Generation --- p.46 / Chapter 3.1.2 --- Analog Placement --- p.49 / Chapter 3.1.3 --- Analog Routing --- p.51 / Chapter 4 --- Analog Placement --- p.53 / Chapter 4.1 --- Introduction --- p.53 / Chapter 4.2 --- Symmetric Feasible Conditions on Sequence Pair --- p.55 / Chapter 4.2.1 --- Properties of Sequence Pair --- p.56 / Chapter 4.2.2 --- Symmetric Feasible Conditions --- p.58 / Chapter 4.3 --- Common Centroid Grid Placement --- p.69 / Chapter 4.3.1 --- Grid Placement Representation --- p.70 / Chapter 4.3.2 --- Common Centroid Feasible Conditions in Grid Sequence --- p.71 / Chapter 4.4 --- Methodology --- p.73 / Chapter 4.4.1 --- Handling Symmetry Constraints --- p.74 / Chapter 4.4.2 --- Device Merging --- p.75 / Chapter 4.4.3 --- Device Clustering --- p.77 / Chapter 4.4.4 --- Enhanced Common Centroid Placement --- p.78 / Chapter 4.4.5 --- Placement Adjustment for Symmetry Groups --- p.82 / Chapter 4.4.6 --- Congestion Aware Placement Expansion --- p.86 / Chapter 4.4.7 --- Types of Moves --- p.87 / Chapter 4.4.8 --- Annealing Schedule and Cost Function --- p.88 / Chapter 5 --- Analog Routing --- p.90 / Chapter 5.1 --- Introduction --- p.90 / Chapter 5.2 --- Methodology --- p.91 / Chapter 5.2.1 --- Symmetry Routing --- p.94 / Chapter 5.2.2 --- Practical Concerns --- p.97 / Chapter 6 --- Layer Assignment --- p.106 / Chapter 6.1 --- Introduction --- p.106 / Chapter 6.1.1 --- Problem Formulation --- p.108 / Chapter 6.1.2 --- Previous Works --- p.109 / Chapter 6.1.3 --- Background --- p.111 / Chapter 6.2 --- Methodology --- p.114 / Chapter 6.2.1 --- Global Conflict-Continuation Graph Construction --- p.114 / Chapter 6.2.2 --- The Modified Two-layer Layer Assignment Scheme --- p.116 / Chapter 6.2.3 --- Stacked Via Problem and Crosstalk --- p.120 / Chapter 6.2.4 --- Max-Cut for planar graph --- p.121 / Chapter 7 --- Experimental Results --- p.128 / Chapter 7.1 --- Results of Analog Placement --- p.129 / Chapter 7.2 --- Results of Layer Assignment --- p.133 / Chapter 7.3 --- Simulation Results --- p.134 / Bibliography --- p.136

Ho, Man Ho. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2011. / Includes bibliographical references (p. 60-64). / Abstracts in English and Chinese. / Abstract --- p.i / Chinese Abstract --- p.iii / Acknowledgement --- p.v / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Motivation --- p.1 / Chapter 1.2 --- Objectives --- p.3 / Chapter 1.3 --- Contributions --- p.4 / Chapter 1.4 --- Thesis Organization --- p.5 / Chapter 2 --- Background Study --- p.6 / Chapter 2.1 --- Introduction --- p.6 / Chapter 2.2 --- Architecture & Design Flows --- p.6 / Chapter 2.3 --- Summary --- p.11 / Chapter 3 --- Architecture --- p.14 / Chapter 3.1 --- Overview --- p.14 / Chapter 3.2 --- Fabric Architecture --- p.15 / Chapter 3.2.1 --- Programmable Layers --- p.15 / Chapter 3.2.2 --- Fabric Organization --- p.16 / Chapter 3.3 --- Logic Block Designs --- p.19 / Chapter 3.3.1 --- Lookup-table (LUT) Based Logic Block --- p.19 / Chapter 3.3.2 --- Static CMOS Style Logic Block --- p.22 / Chapter 3.4 --- Summary --- p.26 / Chapter 4 --- EDA Design Flow --- p.27 / Chapter 4.1 --- Overview --- p.27 / Chapter 4.2 --- Library Preparation --- p.27 / Chapter 4.3 --- Design Synthesis --- p.29 / Chapter 4.4 --- Fabric Creation & Design Mapping Flows --- p.30 / Chapter 4.5 --- Summary --- p.35 / Chapter 5 --- Experimental Results --- p.36 / Chapter 5.1 --- Benchmark Circuits Description --- p.36 / Chapter 5.2 --- Experiment Configurations --- p.37 / Chapter 5.2.1 --- Synthesis --- p.38 / Chapter 5.2.2 --- Placement & Routing --- p.39 / Chapter 5.3 --- Comparison Metrics --- p.40 / Chapter 5.4 --- Area & Critical Path Delay Comparisons --- p.41 / Chapter 5.5 --- Summary --- p.46 / Chapter 6 --- Prototypes Testing --- p.47 / Chapter 6.1 --- Overview --- p.47 / Chapter 6.2 --- Second Tape-out --- p.47 / Chapter 6.2.1 --- Sample Application --- p.48 / Chapter 6.2.2 --- Signoff preparations --- p.50 / Chapter 6.2.3 --- Results for Test unit --- p.51 / Chapter 6.2.4 --- Functional test of Peak unit --- p.52 / Chapter 6.3 --- Third Tape-out --- p.53 / Chapter 6.3.1 --- Test Results . --- p.54 / Chapter 7 --- Conclusion --- p.57 / Chapter 7.1 --- Future Works --- p.58 / Bibliography --- p.59

Qian, Zaichen. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2010. / Includes bibliographical references (leaves 62-67). / Abstracts in English and Chinese. / Abstract --- p.i / Acknowledgement --- p.iii / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- VLSI Design Methodology --- p.1 / Chapter 1.2 --- Low Power Design --- p.6 / Chapter 1.3 --- Literature Review on Multiple Supply Voltage (MSV) --- p.10 / Chapter 1.3.1 --- Voltage Island Partitioning Problems --- p.11 / Chapter 1.3.2 --- Multiple Voltage Assignment (MVA) Problem --- p.12 / Chapter 1.4 --- Literature Review on Dynamic Voltage Scaling and Dynamic Power Management --- p.15 / Chapter 1.4.1 --- Dynamic Voltage Scaling (DVS) Problem --- p.16 / Chapter 1.4.2 --- Dynamic Power Management --- p.20 / Chapter 1.5 --- Thesis Contribution and Organization --- p.22 / Chapter 2 --- Multi-Voltage Floorplan Design --- p.24 / Chapter 2.1 --- Introduction --- p.24 / Chapter 2.2 --- Problem Formulation --- p.26 / Chapter 2.3 --- A Value-Oriented Branch-and-Bound Algorithm --- p.29 / Chapter 2.3.1 --- Branching Rules --- p.30 / Chapter 2.3.2 --- Upper Bounds --- p.31 / Chapter 2.3.3 --- Lower Bounds --- p.32 / Chapter 2.3.4 --- Pruning Rules and Value-Oriented Searching Rules --- p.33 / Chapter 2.4 --- Floorplanning --- p.35 / Chapter 2.5 --- Experimental Results --- p.36 / Chapter 2.5.1 --- Optimal Voltage Assignment --- p.37 / Chapter 2.5.2 --- Floorplanning Results --- p.38 / Chapter 3 --- Low Power Scheduling at System Level --- p.40 / Chapter 3.1 --- Introduction --- p.40 / Chapter 3.2 --- Problem Formulation --- p.42 / Chapter 3.3 --- An Optimal Offline Algorithm --- p.43 / Chapter 3.4 --- Online Algorithm --- p.46 / Chapter 3.4.1 --- Analysis on One Single Interval --- p.46 / Chapter 3.4.2 --- Online Algorithm --- p.49 / Chapter 3.4.3 --- Analysis of the Online Algorithm --- p.52 / Chapter 3.5 --- Experimental Results --- p.56 / Chapter 4 --- Conclusion and Future Work --- p.60 / Bibliography --- p.67