Spelling suggestions: "subject:"entegrated circuits -- 1design"" "subject:"entegrated circuits -- 22design""
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COMPUTER AIDED DESIGN OF INTEGRATED CIRCUITSLillis, William Joseph, 1944- January 1972 (has links)
No description available.
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Modeling and control of extrusion coatingPopescu, Catalin Nicolae 08 1900 (has links)
No description available.
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Field effect transistor noise model analysis and low noise amplifier design for wireless data communicationsYoo, Seungyup 12 1900 (has links)
No description available.
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Low-power, high-accuracy, and fast-tuning integrated continuous-time 450-KHz bandpass filterPham, Tien Ke 12 1900 (has links)
No description available.
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High frequency integrated filters for wireless applicationsKöroğlu, Mustafa Hadi 12 1900 (has links)
No description available.
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Electromagnetic modeling of interconnects incorporating perforated ground planesMathis, Andrew Wiley 08 1900 (has links)
No description available.
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Offset correction in flash ADCs using floating-gate circuitsBrady, Philomena C. 05 1900 (has links)
No description available.
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Highly linear, rail-to-rail ICMR, low voltage CMOS operational ampliferMurty, Anjali 05 1900 (has links)
No description available.
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A floating-gate low dropout voltage regulatorLow, Aichen 05 1900 (has links)
No description available.
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Integrated and Distributed Digital Low-Drop-Out Regulators with Event-Driven Controls and Side-Channel Attack ResistanceKim, Sung Justin January 2021 (has links)
A modern system-on-chip (SoC) integrates a range of analog, digital, and mixed-signal building blocks, each with a dedicated voltage domain to maximize energy efficiency. On-chip low-drop-out regulators (LDOs) are widely used to implement these voltage domains due to their advantages of high power density and the ease of integration to a complementary metal-oxide-semiconductor (CMOS) process. Recently, digital LDOs have gained large attention for their low input voltage support for emerging sub-mW SoCs, portability across designs, and process scalability. However, some of the major drawbacks of a conventional digital LDO design are (i) the trade-off between control loop latency and power dissipation which demands a large output capacitor, (ii) failure to address the performance degradations caused by the parasitics in a practical power grid, and (iii) insufficient power-supply-rejection-ratio (PSRR) and large ripple in the output voltage.
Chapters 2 through 4 of this thesis present my research on the design and circuit techniques for improving the aforementioned challenges in fully-integrated digital LDOs. The first work implements a hybrid event- and time-driven control in the digital LDO architecture to improve the response and settling time-related metrics over the existing designs. The second work presents a power delivery system consisting of 9 distributed event-driven digital LDOs for supporting a spatially large digital load. The proposed distributed LDO design achieves large improvements in the steady-state and non-steady-state performances compared to a single LDO design. In the third work, we prototype a digital LDO based on new current-source power-FETs to achieve a high PSRR and low output voltage ripple.
Lastly, on-chip voltage regulators have recently found usefulness in hardware security applications. An on-chip LDO can be used to improve the side-channel attack (SCA) resistance of a cryptographic core with design modifications to the classical LDO architecture. However, the existing designs incur non-negligible overheads in performance, power, and silicon area due to the conventional active-for-all-encryption-rounds architecture. In the last chapter, we propose a detection-driven activation technique to achieve a near-zero energy-delay-product (EDP) overhead in a SCA resilient digital LDO. In this architecture, the LDO can detect an attack attempt and enable SCA protection only if an attack is detected.
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