In measurement, the entire BBP design with the proposed gate-level structures exhibits high robustness in power supply and frequency variations. It can function normally at a minimum of 0.33 V power supply, which is over 100 mV below typical threshold voltage. In the test of the ACRL circuits, the ACRL cells show 30 - 70% delay reduction when compared to the standard static CMOS cells. And the ACRL custom PIE decoder works at the minimum of 0.26 V power supply, which is 40 mV lower than the minimum operating voltage archived by the PIE decoder in the BBP implemented with standard cells. / In this thesis, methodologies and examples are proposed for subthreshold digital circuit design. There is also a full study on subthreshold characteristics of devices and circuits in very-low-voltage operation. The EPC C1G2 baseband processor (BBP) for passive UHF (ultra high frequency) RFID (radio frequency identification) tag is selected as a subthreshold design example, as it is a digital design typified with instable very low supply voltage and requires ultra low power in operation. To tailor the BBP for lower operating voltage in subthreshold region, optimized structures and topologies are proposed in different hierarchical levels. In the system view, the BBP is partitioned according to the clock domain and the constraints of timing. Go down to the RTL and gate level, pipelining, parallelism, clock gating and one-hot state transition are implemented in the logic design according to the actual requirement. In this way energy awareness and power saving are achieved with enhanced robustness to operate in subthreshold region. The BBP with the proposed logic structures has been fabricated in several deep submicron CMOS technologies. Transistor level design is the bottom level for IC designers, the proposed active control ratioed logic (ACRL) is a logic style with fast pull-up network and less capacitance, particularly suitable for the implementation of high fan-in AOI-familiar (and-or-inverter) structure. Some general ACRL cells designs, 32-bit equality comparator and, a custom PIE decoder with ACRL cells, which is the important block of BBP with critical timing, have been fabricated in 130 nm CMOS technology. / Subthreshold designs are required in many actual applications. Especially, the subthreshold digital systems and circuits have become more and more popular in portable devices and passive systems. In conception subthreshold digital circuits are very-low-voltage circuits, they have great reduction of power consumption but suffer from long logic delay as the driving current for logic transition and propagation is greatly reduced. / Shi, Weiwei. / Adviser: C.S. Choy. / Source: Dissertation Abstracts International, Volume: 73-04, Section: B, page: . / Thesis (Ph.D.)--Chinese University of Hong Kong, 2011. / Includes bibliographical references (leaves 146-152). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Electronic reproduction. [Ann Arbor, MI] : ProQuest Information and Learning, [201-] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstract also in Chinese.

In addition, we can further reduce the power consumption by reducing the number of interconnects. We propose to use a quaternary (4-level) logic output to replace the binary (2-level) logic output, which will reduce the number of interconnect by half. A 6-bit current mode analog-to-quaternary converter (AQC) test chip is designed with special current mode quaternary logic functions. / The power reduction techniques are carried out in both circuit and system levels. At the circuit level, a new sub-stage design using voltage comparator is proposed to reduce power consumption without any performance degradation. At the system level, we observe that the signal-to-noise ratio (SNR) of a current mode pipelined ADC is proportional to the input current level, and the SNR of a pipelined ADC is dominated by the first few stages. Thus, it is possible to reduce the power consumption without significantly degrading the SNR by gradually reducing the current level of each stage along the pipeline. A 12-bit CMOS current mode pipelined ADC test chip is designed with a 0.35mum CMOS digital process. The measured signal-to-noise and distortion ratio (SNDR), spurious free dynamic range (SFDR) and total harmonic distortion (THD) are 64.90dB, 67.79dB and -67.02dB, respectively. The effective number of bit (ENOB) achieved is 10.49-bit and the calculated FOM is 1.31pJ, which has the lowest power consumption among reported current mode ADCs. / The supply voltage of advanced CMOS technology is reduced to 1V or less. It is very difficult to design high performance analog circuit at this supply voltage because of the limited dynamic range. One possible solution is to use current mode circuit technique which is less sensitive to the limited dynamic range. Moreover, current mode circuit is more suitable for low voltage applications compare to the conventional voltage mode circuit. This research uses analog-to-digital converter (ADC) as a vehicle to investigate current mode design techniques with a main focus on power reduction. / Chan Chi Hong. / "September 2007." / Adviser: C. F. Chan. / Source: Dissertation Abstracts International, Volume: 69-08, Section: B, page: 4923. / Thesis (Ph.D.)--Chinese University of Hong Kong, 2007. / Includes bibliographical references. / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Electronic reproduction. [Ann Arbor, MI] : ProQuest Information and Learning, [200-] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstracts in English and Chinese. / School code: 1307.

However, the proposed receiver and channel selection scheme still suffer from the mismatches picked up during RF-to-IF conversion. Therefore, a system called phase and amplitude mismatch cancellers is adopted to deal with the problem. Existing implementations neglected several critical behaviors of the cancellers, and provide image rejection ratios (IRR) ranging from 50dB to 65dB only. These behaviors include (i) arithmetic underflow, (ii) angular obscurity and (iii) spurious intermodulation products (IMD) produced by cancellers. We analyzed them and established several design rules, by which a far better IRR of at least 82.5dB was achieved. The system makes the proposed receiver and channel selection method feasible. / In traditional receivers involving intermediate frequency (IF), two different RF channels, Signal and Image, are converted to the same IF and overlap with each other. The Signal is always wanted with the Image eliminated, so each RF LO frequency can only select one RF channel. By digital low-IF, the IF-to-baseband conversion can be configured so that either channel can be selected, then each RF LO frequency can select two RF channels. This enhanced channel selection scheme can effectively reduce the number of LO frequency locations by half as well as the requirements of RF PLL frequency synthesizer. An existing approach makes use of configurable sampling scheme to achieve the same aim, but its use of analog sampling circuits results in phase and amplitude mismatches, from which the performance of image rejection suffers. Digital low-IF does not have this problem, since no mismatches are introduced to the signals after digitization. / The proposed digital low-IF Weaver receiver, together with the enhanced channel selection scheme and the phase and amplitude mismatch cancellers, are demonstrated to be feasible by a multi-band multi-mode receiver prototype supporting GSM900 and WCDMA. / The receiver architecture proposed in this thesis makes use of Weaver architecture with digital low-IF. Its flexibility allows for any operations to be performed on the digitized signals, as well as the enhanced channel selection scheme proposed in this thesis. / Chan Pak Kee. / "September 2007." / Adviser: Chiu Sing Choy. / Source: Dissertation Abstracts International, Volume: 69-08, Section: B, page: 4924. / Thesis (Ph.D.)--Chinese University of Hong Kong, 2007. / Includes bibliographical references (p. 152-162). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Electronic reproduction. [Ann Arbor, MI] : ProQuest Information and Learning, [200-] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstracts in English and Chinese. / School code: 1307.

Cheung, Cheuk Kit. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2009. / Includes bibliographical references. / Abstract also in Chinese. / Abstract --- p.1 / 摘要 --- p.2 / Acknowledgements --- p.3 / Table of Contents --- p.4 / List of Figures --- p.9 / Chapter 1. --- Introduction --- p.12 / Chapter 1.1. --- Research Motivation --- p.12 / Chapter 1.1.1. --- Global and Intermediate Interconnects --- p.12 / Chapter 1.1.2. --- Constraints of Repeater Insertion Techniques --- p.13 / Chapter 1.2. --- Research Objective --- p.13 / Chapter 1.3. --- Reference --- p.14 / Chapter 2. --- Voltage Mode and Current Mode Circuits --- p.16 / Chapter 2.1. --- Introduction --- p.16 / Chapter 2.2. --- Voltage Mode Circuit --- p.16 / Chapter 2.3. --- Current Mode Circuit --- p.18 / Chapter 2.4. --- Power Consumption --- p.19 / Chapter 2.5. --- Latency --- p.20 / Chapter 2.6. --- Summary --- p.20 / Chapter 3. --- Transmitter Design --- p.22 / Chapter 3.1. --- Introduction --- p.22 / Chapter 3.2. --- Multi-level Signaling --- p.22 / Chapter 3.3. --- Gated Current Mirror --- p.23 / Chapter 3.4. --- Power Consumption --- p.24 / Chapter 3.5. --- Summary --- p.24 / Chapter 3.6. --- Reference --- p.25 / Chapter 4. --- Receiver Design --- p.26 / Chapter 4.1. --- Introduction --- p.26 / Chapter 4.2. --- Conventional Latched-typed Sense Amplifier --- p.27 / Chapter 4.3. --- Sense Amplifier with Isolated Differential Pair --- p.29 / Chapter 4.4. --- "Power Consumption, Latency and Kick-back Noise Comparison between Different Designs" --- p.30 / Chapter 4.4.1. --- Comparison on Power Consumption --- p.30 / Chapter 4.4.2. --- Comparison on Latency --- p.31 / Chapter 4.4.3. --- Comparison on Kick-back Noise --- p.33 / Chapter 4.5. --- Summary --- p.34 / Chapter 4.6. --- Reference --- p.34 / Chapter 5. --- Inverter Chain --- p.36 / Chapter 5.1. --- Introduction --- p.36 / Chapter 5.2. --- Inverter Chain Based --- p.36 / Chapter 5.3. --- Summary --- p.38 / Chapter 5.4. --- References --- p.38 / Chapter 6. --- Layout Techniques --- p.39 / Chapter 6.1. --- Introduction --- p.39 / Chapter 6.2. --- Two-Dimensional Common Centroid Layout Technique --- p.39 / Chapter 6.3. --- Dummy Devices --- p.40 / Chapter 6.4. --- Summary --- p.42 / Chapter 6.5. --- References --- p.42 / Chapter 7. --- Simulation Results --- p.43 / Chapter 7.1. --- Introduction --- p.43 / Chapter 7.2. --- Simulation of Different Aspect Ratios of Differential Pair --- p.43 / Chapter 7.3. --- System Level Simulation with Different Sense-amplifiers --- p.46 / Chapter 7.4. --- System Level Simulation at Different Data Rate --- p.47 / Chapter 7.5. --- Summary --- p.49 / Chapter 8. --- Measurement Results --- p.50 / Chapter 8.1. --- Introduction --- p.50 / Chapter 8.2. --- Experimental Setup --- p.50 / Chapter 8.2.1. --- Testing Chips --- p.50 / Chapter 8.2.2. --- Equipments Setup --- p.52 / Chapter 8.3. --- Measurement Results --- p.53 / Chapter 8.4. --- Summary --- p.56 / Chapter 9. --- Conclusion --- p.57 / Chapter 9.1. --- Author´ةs Contributions --- p.57 / Chapter 9.2. --- Future Works --- p.58 / Chapter 10. --- Appendix --- p.59

Ma, Qiang. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2008. / Includes bibliographical references (leaves 78-80). / Abstracts in English and Chinese. / Abstract --- p.i / Acknowledgement --- p.iv / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Background --- p.1 / Chapter 1.2 --- Floorplanning --- p.2 / Chapter 1.3 --- Motivations --- p.4 / Chapter 1.4 --- Design Implementation of Voltage Islands --- p.5 / Chapter 1.5 --- Problem Formulation --- p.8 / Chapter 1.6 --- Progress on the Problem --- p.10 / Chapter 1.7 --- Contributions --- p.12 / Chapter 1.8 --- Thesis Organization --- p.14 / Chapter 2 --- Literature Review on MSV --- p.15 / Chapter 2.1 --- Introduction --- p.15 / Chapter 2.2 --- MSV at Post-floorplan/Post Placement Stage --- p.16 / Chapter 2.2.1 --- """Post-Placement Voltage Island Generation under Performance Requirement""" --- p.16 / Chapter 2.2.2 --- """Post-Placement Voltage Island Generation""" --- p.18 / Chapter 2.2.3 --- """Timing-Constrained and Voltage-Island-Aware Voltage Assignment""" --- p.19 / Chapter 2.2.4 --- """Voltage Island Generation under Performance Requirement for SoC Designs""" --- p.20 / Chapter 2.2.5 --- """An ILP Algorithm for Post-Floorplanning Voltage-Island Generation Considering Power-Network Planning""" --- p.21 / Chapter 2.3 --- MSV at Floorplan/Placement Stage --- p.22 / Chapter 2.3.1 --- """Architecting Voltage Islands in Core-based System-on-a- Chip Designs""" --- p.22 / Chapter 2.3.2 --- """Voltage Island Aware Floorplanning for Power and Timing Optimization""" --- p.23 / Chapter 2.4 --- Summary --- p.27 / Chapter 3 --- MSV Driven Floorplanning --- p.29 / Chapter 3.1 --- Introduction --- p.29 / Chapter 3.2 --- Problem Formulation --- p.32 / Chapter 3.3 --- Algorithm Overview --- p.33 / Chapter 3.4 --- Optimal Island Partitioning and Voltage Assignment --- p.33 / Chapter 3.4.1 --- Voltage Islands in Non-subtrees --- p.35 / Chapter 3.4.2 --- Proof of Optimality --- p.36 / Chapter 3.4.3 --- Handling Island with Power Down Mode --- p.37 / Chapter 3.4.4 --- Speedup in Implementation and Complexity --- p.38 / Chapter 3.4.5 --- Varying Background Chip-level Voltage --- p.39 / Chapter 3.5 --- Simulated Annealing --- p.39 / Chapter 3.5.1 --- Moves --- p.39 / Chapter 3.5.2 --- Cost Function --- p.40 / Chapter 3.6 --- Experimental Results --- p.40 / Chapter 3.6.1 --- Extension to Minimize Level Shifters --- p.45 / Chapter 3.6.2 --- Extension to Consider Power Network Routing --- p.46 / Chapter 3.7 --- Summary --- p.46 / Chapter 4 --- MSV Driven Floorplanning with Timing --- p.49 / Chapter 4.1 --- Introduction --- p.49 / Chapter 4.2 --- Problem Formulation --- p.52 / Chapter 4.3 --- Algorithm Overview --- p.56 / Chapter 4.4 --- Voltage Assignment Problem --- p.56 / Chapter 4.4.1 --- Lagrangian Relaxation --- p.58 / Chapter 4.4.2 --- Transformation into the Primal Minimum Cost Flow Problem --- p.60 / Chapter 4.4.3 --- Cost-Scaling Algorithm --- p.64 / Chapter 4.4.4 --- Solution Transformation --- p.66 / Chapter 4.5 --- Simulated Annealing --- p.69 / Chapter 4.5.1 --- Moves --- p.69 / Chapter 4.5.2 --- Speeding up heuristic --- p.69 / Chapter 4.5.3 --- Cost Function --- p.70 / Chapter 4.5.4 --- Annealing Schedule --- p.71 / Chapter 4.6 --- Experimental Results --- p.71 / Chapter 4.7 --- Summary --- p.72 / Chapter 5 --- Conclusion --- p.76 / Bibliography --- p.80

Jiang, Li. / "October 2010." / Thesis (M.Phil.)--Chinese University of Hong Kong, 2010. / Includes bibliographical references (leaves 71-76). / Abstracts in English and Chinese. / Abstract --- p.i / Acknowledgement --- p.ii / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Three Dimensional Integrated Circuit --- p.1 / Chapter 1.1.1 --- 3D ICs --- p.1 / Chapter 1.1.2 --- Manufacture --- p.3 / Chapter 1.2 --- Test Architecture Design and Optimization for SoCs --- p.4 / Chapter 1.2.1 --- Test Wrapper --- p.4 / Chapter 1.2.2 --- Test Access Mechanism --- p.6 / Chapter 1.2.3 --- Test Architecture Optimization and Test Scheduling --- p.7 / Chapter 1.3 --- Thesis Motivation and Organization --- p.9 / Chapter 2 --- On Test Time and Routing Cost --- p.12 / Chapter 2.1 --- Introduction --- p.12 / Chapter 2.2 --- Preliminaries and Motivation --- p.13 / Chapter 2.3 --- Problem Formulation --- p.17 / Chapter 2.3.1 --- Test Cost Model --- p.17 / Chapter 2.3.2 --- Routing Model --- p.17 / Chapter 2.3.3 --- Problem Definition --- p.19 / Chapter 2.4 --- Proposed Algorithm --- p.22 / Chapter 2.4.1 --- Outline of The Proposed Algorithm --- p.22 / Chapter 2.4.2 --- SA-Based Core Assignment --- p.24 / Chapter 2.4.3 --- Heuristic-Based TAM Width Allocation --- p.25 / Chapter 2.4.4 --- Fast routing Heuristic --- p.28 / Chapter 2.5 --- Experiments --- p.29 / Chapter 2.5.1 --- Experimental Setup --- p.29 / Chapter 2.5.2 --- Experimental Results --- p.31 / Chapter 2.6 --- Conclusion --- p.34 / Chapter 3 --- Pre-bond-Test-Pin Constrained Test Wire Sharing --- p.37 / Chapter 3.1 --- Introduction --- p.37 / Chapter 3.2 --- Preliminaries and Motivation --- p.38 / Chapter 3.2.1 --- Prior Work in SoC Testing --- p.38 / Chapter 3.2.2 --- Prior Work in Testing 3D ICs --- p.39 / Chapter 3.2.3 --- Test-Pin-Count Constraint in 3D IC Pre-Bond Testing --- p.40 / Chapter 3.2.4 --- Motivation --- p.41 / Chapter 3.3 --- Problem Formulation --- p.43 / Chapter 3.3.1 --- Test Architecture Design under Pre-Bond Test-Pin-Count Constraint --- p.44 / Chapter 3.3.2 --- Thermal-aware Test Scheduling for Post-Bond Test --- p.45 / Chapter 3.4 --- Layout-Driven Test Architecture Design and Optimization --- p.46 / Chapter 3.4.1 --- Scheme 1: TAM Wire Reuse with Fixed Test Architectures --- p.46 / Chapter 3.4.2 --- Scheme 2: TAM Wire Reuse with Flexible Pre-bond Test Architecture --- p.52 / Chapter 3.5 --- Thermal-Aware Test Scheduling for Post-Bond Test --- p.53 / Chapter 3.5.1 --- Thermal Cost Function --- p.54 / Chapter 3.5.2 --- Test Scheduling Algorithm --- p.55 / Chapter 3.6 --- Experimental Results --- p.56 / Chapter 3.6.1 --- Experimental Setup --- p.56 / Chapter 3.6.2 --- Results and Discussion --- p.58 / Chapter 3.7 --- Conclusion --- p.59 / Chapter 3.8 --- Acknowledgement --- p.60 / Chapter 4 --- Conclusion and Future Work --- p.69 / Bibliography --- p.70

Or, Pui Ying. / "July 2010." / Thesis (M.Phil.)--Chinese University of Hong Kong, 2010. / Includes bibliographical references. / Abstracts in English and Chinese. / Acknowledgments / Table of Content / List of Figures / List of Tables / List of Publications / Chapter Chapter 1 - --- Background of LDO Research / Chapter 1.1 --- Structure of a LDO --- p.1-1 / Chapter 1.2 --- Principle of Operation of LDO --- p.1-2 / Chapter 1.3 --- Steady-State Specification of LDO --- p.1-3 / Chapter 1.4 --- High-Frequency Specification of LDO --- p.1-3 / Chapter 1.5 --- Dynamic Specification of LDO --- p.1-4 / Chapter 1.6 --- An Advanced LDO Structure --- p.1-4 / Chapter 1.7 --- Contribution and Outline of the Thesis --- p.1-5 / References --- p.1-6 / Chapter Chapter 2 - --- PSRR Analysis / Chapter 2.1 --- Modeling of the PSRR of LDO --- p.2-3 / Chapter 2.2 --- Analysis of LDO Circuit Using Proposed Modeling --- p.2-6 / Chapter 2.3 --- Conclusion of Chapter --- p.2-12 / References --- p.2-13 / Chapter Chapter 3- --- An Output-Capacitorless LDO with Direct Voltage-Spike Detection / Chapter 3.1 --- Analysis of Output-Capacitorless LDO --- p.3-5 / Chapter 3.2 --- LDO with Proposed Voltage-Spike Detection Circuit --- p.3-7 / Chapter 3.3 --- Experimental Results --- p.3-15 / Chapter 3.4 --- Conclusion of Chapter --- p.3-21 / References --- p.3-22 / Chapter Chapter 4 - --- A LDO with Impedance Adjustment and Loop-Gain Boosting Technique / Chapter 4.1 --- Proposed LDO --- p.4-3 / Chapter 4.2 --- Experimental Results --- p.4-7 / Chapter 4.3 --- Comparison --- p.4-11 / Chapter 4.4 --- Conclusion of Chapter --- p.4-12 / Reference --- p.4-13 / Chapter Chapter 5 - --- Conclusion and Future Work

Silicon based integrated circuit (IC) technology is approaching its physical limits. For sub 10nm technology nodes, the carbon nanotube (CNT) based field effect transistor has emerged as a promising device because of its excellent electronic properties. One of the major challenges faced by the CNT technology is the unwanted growth of metallic tubes. At present, there is no known CNT fabrication technology which allows the fabrication of 100% semiconducting CNTs. The presence of metallic tubes creates a short between the drain and source terminals of the transistor and has a detrimental impact on the delay, static power and yield of CNT based gates. This thesis will address the challenge of designing robust carbon nanotube based circuits in the presence of metallic tubes. For a small percentage of metallic tubes, circuit level solutions are proposed to increase the functional yield of CNT based gates in the presence of metallic tubes. Accurate analytical models with less than a 3% inaccuracy rate are developed to estimate the yield of CNT based circuit for a different percentage of metallic tubes and different drive strengths of logic gates. Moreover, a design methodology is developed for yield-aware carbon nanotube based circuits in the presence of metallic tubes using different CNFET transistor configurations. Architecture based on regular logic bricks with underlying hybrid CNFET configurations are developed which gives better trade-offs in terms of performance, power, and functional yield. In the case when the percentage of metallic tubes is large, the proposed circuit level techniques are not sufficient. Extra processing techniques must be applied to remove the metallic tubes. The tube removal techniques have trade-offs, as the removal process is not perfect and removes semiconducting tubes in addition to removing unwanted metallic tubes. As a result, stochastic removal of tubes from the drive and fanout gate(s) results in large variation in the performance of CNFET based gates and in the worst case open circuit gates. A Monte Carlo simulation engine is developed to estimate the impact of the removal of tubes on the performance and power of CNFET based logic gates. For a quick estimation of functional yield of logic gates, accurate analytical models are developed to estimate the functional yield of logic gates when a fraction of the tubes are removed. An efficient tube level redundancy (TLR) is proposed, resulting in a high functional yield of carbon nanotube based circuits with minimal overheads in terms of area and power when large fraction of tubes are removed. Furthermore, for applications where parallelism can be utilized we propose to increase the functional yield of the CNFET based circuits by increasing the logic depth of gates.

The thesis presents a new approach to the decomposition of incompletely specified functions and its application to FPGA (Field Programmable Gate Array) mapping. Five methods: Variable Partitioning, Graph Coloring, Bond Set Encoding, CLB Reusing and Local Transformation are developed in order to efficiently perform decomposition and FPGA (Lookup-Table based FPGA) mapping. 1) Variable Partitioning is a high quality hemistic method used to find the "best" partitions, avoiding the very time consuming testing of all possible decomposition charts, which is impractical when there are many input variables in the input function. 2) Graph Coloring is another high quality heuristic\ used to perform the quasi-optimum don't care assignment, making the program possible to accept incompletely specified function and perform a quasi-optimum assignment to the unspecified part of the function. 3) Bond Set Encoding algorithm is used to simplify the decomposed blocks during the process of decomposition. 4) CLB Reusing algorithm is used to reduce the number of CLBs used in the final mapped circuit. 5) Local Transformation concept is introduced to transform nondecomposable functions into decomposable ones, thus making it possible to apply decomposition method to FPGA mapping. All the above developed methods are incorporated into a program named TRADE, which performs global optimization over the input functions. While most of the existing methods recursively perform local optimization over some kinds of network-like graphs, and few of them can handle incompletely specified functions. Cube calculus is used in the TRADE program, the operations are global and very fast. A short description of the TRADE program and the evaluation of the results are provided at the_ end of the thesis. For many benchmarks the TRADE program gives better results than any program published in the literature.

It is important to have the ability to predict the effects of device model variation when designing integrated transconductance-C type active filters. Applying these filters to integrated circuit design has become increasingly popular due to its ease of implementation in monolithic form. With the introduction of fully automated design tools, predictable behavior of high-level variables becomes still more important. The purpose of this study is to evaluate the process parameter spread of analog device models to determine the effect on the design parameters of an active filter. This information's significant contribution directly effects the feasibility and realization of automating analog filter design. In order to explore the dependence of filter performance on the device v model parameter spread, a fifth-order inverse Chebyshev filter is designed and simulated using a two year history of process models. It has not been observed that higher order filters have been successfully designed using fully automated design tools. This filter was realized using automated filter design currently being developed in parallel with this study. A single-ended input to single-ended output transconductance amplifier is chosen for this design for its simplicity and small size. Differential performance is easily adapted with exact duplication which is demonstrated in the measurements of the fabricated filter. Simulation of the design is performed using MOSIS SCNA device parameters. Filter performance data such as cutoff frequency, stopband attenuation, and phase response is collected. Experimental results from the fabricated device are compared to simulation and the original prototype. 2 It is shown that the most predicable effect on the design parameters of a filter is caused by the parasitic output conductance parameter g0. This process dependent variable causes both a deviation in the cutoff frequency, and a decrease in the filter quality factor. In addition, it is also shown that the practice employed to predistort for absorption of parasitic capacitors in a MOS technology is a very effective tool in the reduction of capacitive process dependence.n software