A new circuit technique called Folded Source Coupled Logic (FSCL) has been developed to implement the digital section of mixed-signal IC applications. This FSCL circuit technique offers the advantage of low overlap current spikes during the switching transitions of conventional CMOS gates. This overlap current spike has become one of the major obstacles in improving the accuracy and performance of mixed-signal IC applications. Using simple circuits, FSCL logic family can be interfaced with the existing CMOS family. Thus it can nearly eliminate the power noise issue in the mixed-signal IC design. In this thesis, design of a sinc3 decimation filter using the FSCL technique for a 2nd order delta-sigma modulator has been presented. Simulation results show that this particular decimation filter, using the newly developed FSCL technique, improves the performance of the mixed-signal system. / Graduation date: 1994

Present day data processing technology requires very high speed signal processing and data conversion rates. One such application which requires high speed is switched capacitor circuits used in Sigma-Delta modulators. A major active component of switched capacitor circuits is the monolithic operational amplifier(opamp). Because of the relatively poor speed performance of the currently available silicon based technology, such high speed circuits can not be designed. GaAs technology appears to be a promising alternative technology for high speed switched capacitor circuits. One problem with GaAs is the lack of complementary technology. Until now, most of the design of GaAs analog integrated circuits has been implemented using depletion mode n-MESFETs, where operational amplifiers and switched capacitors have been developed by various groups. This thesis develops the techniques for implementation of analog integrated circuits using complementary GaAs Heterojunction Field Effect Transistors(HFETs). Several operational amplifiers have been designed and their performance studied via simulation. The designs studied predict superior high frequency performance for C-HFETs over conventional GaAs MESFET and Silicon CMOS technology. The opamp designs are currently being implemented at Oregon State University for fabrication in the future. / Graduation date: 1993

Present day data processing technology requires very high speed signal processing and data conversion rates. Traditionally, these circuits have been implemented in silicon MOS technology, whose high speed performance is limited, due to inherent material properties. Though relatively immature compared to silicon technology, GaAs integrated circuit technology appears to be a potential vehicle for realizing high-speed circuits because of its high electron mobility and low parasitic capacitance. One major drawback of GaAs technology has been the lack of complementary technology in contrast to silicon where CMOS technology has greatly facilitated the development of analog ICs. This thesis investigates the suitability of complementary GaAs Heterojunction FET integrated circuit technology for the realization of high sample-rate switched-capacitor circuits. In order to yield an accurate device model for the design work, model parameters of both n and p GaAs Heterojunction FET devices are extracted from measurement results. Based on the extraction results, a set of analog building blocks are presented. These circuits include a high bandwidth operational amplifier and a fast settling switch which are essential for high sample-rate circuits. A second order switched-capacitor low pass filter sampling at a clock rate of 100MHz is designed using the above building blocks. The designs studied predict better high frequency performance for C-HFETs compared to Si CMOS technology. / Graduation date: 1994

dimensional integrated circuits (3D ICs) fabricated with through-silicon vias (TSVs) have smaller planar dimensions, shorter wire length, and better performance than 2D ICs. Heat dissipation causing temperature increase has posed new challenges for design of 3D integrated circuits (IC). In addition to the thermal problem, 3D ICs also require careful design of power grids/network because many inter-tier resistive through-silicon vias in 3D IC can cause larger voltage drop than 2D ICs. The performance optimization of a 3D stack requires validation of thermal and electrical integrity during the co-design. Many 3D stacks will combine digital and analog circuitry, requiring a strong mixed-signal design approach. This will require close collaboration between different domains of circuit fabrication which traditionally have been working separately. Hence there must be some standards to facilitate smooth and effective design of 3D ICs. In this thesis, we perform steady-state electrical and thermal simulations to analyze the properties of a 3D stack. We optimize electrical and thermal performance using genetic algorithm to achieve optimized power map profile for minimizing voltage drop and temperature, which can benefit both thermal and power integrity management. This thesis presents initial efforts in designing such standards. Steady state electrical and thermal simulations are performed to demonstrate the necessary information that needs to be exchanged between the dies to ensure adequate co-design. The main purpose of a Design Exchange Format (DEF) between dies is to permit sharing of information necessary for design by external parties without disclosing their intellectual property (IP). The requirements of the standards should be the minimum necessary to produce satisfactory answers. Producing such models is just a customer support function. The role of the standards is to facilitate the transfer of information through a compact model, not necessarily to build one.

A theory of the sub-ambient fluid pressure phenomenon observed during the wet sliding of a disk on a polymeric pad is presented. Two-dimensional fluid pressure mapping using membrane pressure sensors reveals a large, asymmetrical sub-ambient pressure region occupying about 70 percent of the disk-pad contact area. At the same time, a small positive pressure region exists near the trailing edge of the disk. This phenomenon is believed to be present during chemical mechanical polishing (CMP) and can contribute to the contact pressure, affecting the material removal rate and removal uniformity. Depending on the load and pad speed, the real contact pressure can be more than 2 times the nominal contact pressure due to the applied load. Tilt measurements of the disk carried out by a capacitive sensing technique indicate that the disk is tilted towards the leading edge and pad center when the pad is rotating. In addition, wafer bow is found to be less than 2 m and wafer tilt with respect to the wafer carrier is 5 to 7 m in the CMP configuration. A two-dimensional mixed-lubrication model based on the Reynolds equation is developed and solved using a finite differencing scheme. The pad is modeled as two layers: a top asperity layer described by the Greenwood and Williamson equation, and the bulk pad as linearly elastic. The orientation of the disk is determined by balancing the fluid and solid forces acting on it and solving using a modified Newtons method. It is found that the tilt of the disk and the pad topography play important roles in the distribution of fluid pressure through affecting the film thickness distribution. For a pad with severe topography, minimum and maximum fluid pressures of -90 kPa and +51 kPa respectively are detected. The model is able to recreate the experimental pressure maps. A material removal rate model based on mechanical abrasion and statistics has also been developed. Comparisons of model predictions and silicon oxide polishing results show agreement.

No description available.

published_or_final_version / Electrical and Electronic Engineering / Doctoral / Doctor of Philosophy

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Power minimization in wireless transceivers has become increasingly critical in recent years with the emergence of standards for short-distance applications in the 900 MHz and 2.4 GHz industrial, scientific and medical (ISM) radio bands. The demand for long battery life and better portability in such applications has led to extensive research on low power radio architectures. This dissertation introduces receiver topologies for low-power systems and presents a theoretical performance analysis of the topologies. Two fully integrated receiver down-converters that demonstrate the concept are implemented in a 0.13-[mu]m CMOS technology. These topologies employ merged mixers and IF amplifiers in order to reduce power dissipation for a given dynamic range performance. In the described topologies, the input stage of a mixer is used to simultaneously provide conversion gain and baseband amplification. This is achieved by applying the down-converted IF signal to input of the mixer. Consequently, the effective conversion gain of the design is greatly enhanced with current requirement primarily determined by the input transconductor. Potential degradation mechanisms related to instability and second-order distortion are identified and solved by the use of appropriate circuit techniques. Noise and linearity performance of the down-converters is analyzed and compared to that of conventional cascaded design counterparts. The potential for enhancement of IIP3 performance through cancellation of nonlinear products is discussed. Potential extensions of the above work including feedback-based architectures that exploit multiple loops for further maximizing the power efficiency of receiver front-ends are also presented.