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Predictive methodologies for substrate parasitic extraction and modeling in heavily doped CMOS substratesSharma, Ajit 31 July 2003 (has links)
This thesis presents an automated methodology to calibrate the substrate
profile for accurate prediction of substrate parasitics using Green's function based
extractors. The technique requires fabrication of only a few test structures and results
in an accurate three layered approximation of a heavily doped epitaxial silicon
substrate. The obtained substrate resistances are accurate to about 10% of measurements.
Advantages and limitations of several common measurement techniques
used to measure substrate z-parameters and resistances are discussed. A new and
accurate z-parameter based macro-model has been developed that can be used up
to a few GHz for P��� for contacts that are as close as 2��m. This enhanced model also
addresses the limitations of previous models with regards to implementation aspects
and ease of integration in a CAD framework. Limitations of this modeling approach
have been investigated. The calibration methodology can be used along with the
scalable macromodel for a qualitative pre-design and pre-layout estimation of the
digital switching noise that couples though the substrate to sensitive analog/RF
circuits. / Graduation date: 2004
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Contributions to substrate noise due to supply coupling and pin parasiticsAdluri, Sirisha 14 November 2003 (has links)
Graduation date: 2004
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Power supply noise analysis for 3D ICs using through-silicon-viasSane, Hemant 13 January 2010 (has links)
3D design is being recognized widely as the next BIG thing in system integration. However, design and analysis tools for 3D are still in infancy stage. Power supply noise analysis is one of the critical aspects of a design. Hence, the area of noise analysis for 3D designs is a key area for future development. The following research presents a new parasitic RLC modeling technique for 3D chips containing TSVs as well as a novel optimization algorithm for power-ground network of a 3D chip with the aim of minimizing noise in the network. The following work also looks into an existing commercial IR drop analysis tool and presents a way to modify it with the aim of handling 3D designs containing TSVs.
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Modeling of power supply noise in large chips using the finite difference time domain methodChoi, Jinseong 12 1900 (has links)
No description available.
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