Thesis (M.S.)--University of North Texas, May, 2008. / Title from title page display. Includes bibliographical references.

Thesis (Ph. D.)--University of Texas at Austin, 1999. / Vita. Includes bibliographical references (leaves 189-199). Available also in a digital version from Dissertation Abstracts.

Thesis (Ph. D.)--West Virginia University, 2000. / Title from document title page. Document formatted into pages; contains xiv, 198 p. : ill. (some col.). Vita. Includes abstract. Includes bibliographical references (p. 187-193).

Thesis (Ph.D.) - University of Queensland, 2006. / Includes bibliography.

The advance of internet applications, such as video streaming, big data and cloud computing, is reshaping the telecommunication and internet industries. Bandwidth demands in datacentres have been boosted by these emerging data-hungry internet applications. Regarding inter- and intra-datacentre communications, fine-grained data need to be exchanged across a large shared memory space. Large-scale high-speed optical switches tend to use a rearrangeably non-blocking architecture as this limits the number of switching elements required. However, this comes at the expense of requiring more sophisticated route selection within the switch and also some forms of time-slotted protocols. The looping algorithm is the classical routing algorithm to set up paths in rearrangeably non-blocking switches. It was born in the electronic switch era, where all links in the switches are equal. It is, therefore, not able to accommodate loss difference between optical paths due to the different length of waveguides and distinct numbers of crossings, and bends, leading to sub-optimal performance. We, therefore, propose an advanced path-selection algorithm based on the looping algorithm that minimises the path-dependent loss. It explores all possible set-ups for a given connection assignment and selects the optimal one. It guarantees that no individual path would have a sufficiently substantial loss, therefore, improve the overall performance of the switch. The performance of the proposed algorithm has been assessed by modelling switches using the VPI simulator. An 8×8 Clos-tree switch demonstrates a 2.7dB decrease in loss and 1.9dB improvement in IPDR with 1.5 dB penalty for the worst case. An 8×8 dilated Beneš shows more than 4 dB loss reduction for the lossiest path and 1.4 dB IPDR improvement for 1 dB power penalty. The improved algorithm can be run once for each switch design and store its output in a compact lookup table, enabling rapid switch reconfiguration. Microelectromechanical systems (MEMS) based optical switches have been fabricated with over 1,000 ports which meet the port count requirements in data centre networks. However, the reconfiguration speed of the MEMS switches is limited to the millisecond to microsecond timescale, which is not sufficient for packet switching in datacentres. Opto-electronic devices, such as Mach-Zehnder Interferometers (MZIs) and semiconductor optical amplifiers (SOAs) with nanosecond response time show the potential to fulfil the requirements of packet switching. However, the scalability of MZI switches is inherently limited by insertion loss and accumulated crosstalk, while the scalability of SOA switches is restricted by accumulated noise and distortion. We, therefore, have proposed a dilated Beneš hybrid MZI-SOA design, where MZIs are implemented as 1×2 or 2×1 low-loss switching elements, minimising crosstalk by using a single input, and where short SOAs are included as gain or absorption units, offering either loss compensation or crosstalk suppression though adding only minimal noise and distortion. A 4×4 device has been fabricated and exhibits a mere 1.3dB loss, an extinction ratio of 47dB, and more than 13dB IPDR for a 0.5dB power penalty. When operating with 10 Gb/s per port, 6pJ/bit energy consumption is demonstrated, delivering 20% reduced energy consumption compared with SOA-based switches. The tolerance of the current control accuracy of this switch is very broad. Within a 5 mA bias current range, the power penalty can be maintained below 0.2 dB for 8 dB IPDR and 12 mA for 10 dB IPDR with a penalty less 0.5 dB. The excellent crosstalk and power penalty performance demonstrated by this chip enable the scalability of this hybrid approach. The performance of 16×16 port dilated Beneš hybrid switch is experimentally assessed by cascading 4×4 switch chips, demonstrating an IPDR of 15 dB at a 1 dB penalty with a 0.6 dB power penalty floor. In terms of switches with port count larger than 16×16, the power penalty performance has been analysed with physical layer simulations fitted with state-of-the-art data. We assess the feasibility of three potential topologies, with different architectural optimisations: dilated Beneš, Beneš and Clos-Beneš. Quantitative analysis for switches with up to 2048 ports is presented, achieving a 1.15dB penalty for a BER of 10-3, compatible with soft-decision forward error correction.

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Beams of light carrying orbital angular momentum, such as vortex beams, have many applications in imaging and micromanipulation. We focus on applications in communication, in particular for quantum key distribution, where the security of communication channels is enhanced with the laws of quantum mechanics. However, this procedure requires superpositions of vortex beams. We want to generate such beams using integrated optics components due to their small size and their advantages in scalability and stability. Angular gratings, which are ring resonators with an embedded Bragg grating, are integrated structures known to generate vortex beams. We propose that a ring resonator with two embedded Bragg gratings, each on the inner and outer sidewalls, would generate a superposition of vortex beams. We verify this claim through analytical models, simulations and experiments.

Quantum systems’ integration in chip-scale photonic circuits is the most promising way to succeed in scaling up complex systems for applications ranging from quantum computation to secure communications. Large systems with many components, especially for scaled all-optical quantum or classical processors, will require improved building blocks with greatly reduced loss, and enhanced bandwidth and robustness to fabrication uncertainties, temperature, etc. In this work, we introduce the concept of rapid adiabatic mode evolution that is the basis of a new family of passive devices with fundamentally improved performance, that we refer to as rapid adiabatic devices. In conventional adiabatic devices, a concept well known in photonics, the waveguide cross-section slowly evolves along the propagation direction, with no particular attention paid to transverse positioning of the cross-section. In contrast, in rapid adiabatic devices, we control the transverse position evolution (taking a tailored off-axis path while advancing along the direction of propagation). This has a major impact on the dominant crosstalk mechanism, the limiting factor to all performance metrics. By judicious synthesis and design, the dominant crosstalk coupling mechanism can be minimized or even set to zero everywhere along the structure. This concept brings a new paradigm to photonic passives that we stand the test of time as an important tool in the integrated photonics tool-box. We experimentally demonstrate a new integrated 2×2 beam splitter design we call a Rapid Adiabatic Coupler (RAC) in different fabrication platforms. The design is implemented in state-of-the art, field-leading CMOS photonics platforms pioneered in our group, taking into account foundry-imposed limitations on design. It nevertheless shows field-leading, very low-loss and extremely broadband 50:50 splitting ratio over hundreds of nanometers of optical bandwidth. In addition, we also demonstrate other photonic passives based on the concept – Rapid Adiabatic Crossings (RAX), a Rapid Adiabatic Mode Splitter (RAMS) as well as a Polarization Splitter Rotator based on the RAMS. These new high performance, compact components will enable larger-scale systems on chip with a higher number of components, not only for quantum photonics applications but also for other types of systems for sensing, optical AI accelerators, optical “FPGAs”, optical switches and routers, optical communication links and others. Another key building block for quantum photonic systems is integrated single photon sources. Following the first demonstration of a pair source integrated with pump filters by our group, here we demonstrate a monolithically integrated tunable photon pair source and pump filter on chip in a commercial, advanced 45nm CMOS microelectronics process. Next, we propose electronic-photonic quantum systems on chip, that contain monolithically integrated electronics and photonic components, as a platform to further scale up complexity in, and modularize, quantum systems on chip. As a first demonstration concept, we propose and demonstrate the first experimental step toward a “wall-plug” photon pair source implemented as an electronic-photonic monolithic chiplet. The idea is a CMOS die (or electronic-photonic block on the chip) that takes only electrical DC power, optical CW laser “DC power”, and control signals, and generates high quality photon pairs. The system contains a thermally tunable second-order filter with heater drivers integrated in the chiplet electronics to clean the input pump laser, a self-locking source ring with integrated electronic circuits that allow the ring resonance to automatically align to the pump laser and low-loss, high extinction, high-order thermally tunable filters. These results taken together show that monolithic integration in CMOS micro-electronics processes does allow high performance photonics, while also supporting scalable complex circuits with electronic control to account for the extreme sensitivity of photonic components and impart reconfigurability and tunability; showing it as a viable approach to build large-scale electronic-photonic systems with a realistic path to commercial technologies. This work was supported in part by the NSF RAISE-EQuIP program (Award 1842692) and by the Packard Foundation (Award 2012-38222). / 2023-05-23T00:00:00Z

No description available.

No description available.