In a VLSI design environment, a more efficient test generation algorithm is definitely needed. This thesis evaluates a test generation algorithm, PODEM, as mechanism to generate the goal states in a sequential circuit test search system, SCIRTSS. First, a hardware description language, AHPL, is used to describe the behavior of a sequential circuit. Next, SCIRTSS is used to generate the test vectors. Several circuits are evaluated and experimental results are compared with data from a previous version of SCIRTSS which was implemented with the D-Algorithm. Depending on the number of reconvergent fanouts in a circuit, it is found that PODEM is 1 to 23 times faster than the D-Algorithm.

A programação orientada a aspectos é uma abordagem que utiliza conceitos da separação de interesses para modularizar o software de maneira mais adequada. Com o surgimento dessa abordagem vieram também novos desafios, dentre eles o teste de programas orientados a aspectos. Duas estratégias de ordenação de classes e aspectos para apoiar o teste de integração orientado a aspectos são propostas nesta tese. As estratégias de ordenação tem o objetivo de diminuir o custo da atividade de teste por meio da diminuição do número de stubs implementados durante o teste de integração. As estratégias utilizam um modelo de dependências aspectuais e um modelo que descreve dependências entre classes e aspectos denominado AORD (Aspect and Oriented Relation Diagram) também propostos neste trabalho. Tanto o modelo de dependências aspectuais como o AORD foram elaborados a partir da sintaxe e semântica da linguagem AspectJ. Para apoiar as estratégias de ordenação, idealmente aplicadas durante a fase de projeto, um processo de mapeamento de modelos de projeto que usam as notações UML e MATA para o AORD é proposto neste trabalho. O processo de mapeamento é composto de regras que mostram como mapear dependências advindas da programação orientada a objetos e também da programação orientada a aspectos. Como uma forma de validação das estratégias de ordenação, do modelo de dependências aspectuais e do AORD, um estudo exploratório de caracterização com três sistemas implementados em AspectJ foi conduzido. Durante o estudo foram coletadas amostras de casos de implementação de stubs e drivers de teste. Os casos de implementação foram analisados e classificados. A partir dessa análise e classificação, um catálogo de stubs e drivers de teste é apresentado / Aspect-oriented programming is an approach that uses principles of separation of concerns to improve the sofware modularization. Testing of aspect-oriented programs is a new challenge related to this approach. Two aspects and classes test order strategies to support integration testing of aspect-oriented programs are proposed in this thesis. The objective of these strategies is to reduce the cost of testing activities through the minimization of the number of implemented stubs during integration test. An aspectual dependency model and a diagram which describes dependencies among classes and aspects called AORD (Aspect and Object Relation Diagram) used by the ordering strategies are also proposed. The aspectual dependency model and the AORD were defined considering the syntax constructions and the semantics of AspectJ. As the proposed estrategies should be applied in design phase of software development, a process to map a desing model using UML and MATA notations into a AORD is proposed in order to support the ordering strategies. The mapping process is composed by rules that show how to map both aspect and object-oriented dependencies. A characterization exploratory study using three systems implemented with AspectJ was conducted to validate the ordering strategies, the aspectual dependency model and the AORD. Interesting samples of stubs implementations were collected during the study conduction. The stubs were analyzed and classified. Based on these analysis and classification a catalog of stubs and drivers is presented

Um dos pontos fundamentais na atividade de teste de software é o projeto de casos de teste. Diversos critérios de adequação têm sido propostos com o objetivo de fornecer meios que permitam que a avaliação e elaboração de casos de teste sejam feitas de maneira sistemática e fundamentadas teoricamente. Infelizmente, a maioria dos critérios de adequação de casos de teste definidos tem seu uso restrito ao teste de unidade. Para fases posteriores da atividade de teste, em particular para o teste de integração, nota-se a ausência de critérios de adequação, principalmente porque os critérios propostos definem requisitos de teste que se restringem aos limites de uma única unidade, não exercitando de maneira efetiva as interações entre as unidades, que devem ser alvo principal no teste de integração. Com exceção de alguns poucos trabalhos que procuram estender critérios estruturais para o nível interprocedimental, tem-se utilizado nessa fase de teste, quase que exclusivamente, critérios funcionais. Dada essa ausência de critérios e salientando ainda o caráter complementar entre as diferentes técnicas de teste, esta tese apresenta um critério de teste interprocedimental baseado em defeitos chamado de Mutação de Interface. Esse critério busca exercitar as interações entre as unidades através da seleção de casos de teste que distingam mutantes criados pela introdução de defeitos típicos e que, de acordo com um modo definido, caracterizamos erros de integração. Definiu-se um conjunto de operadores de Mutação de Interface que concentram sua aplicação em pontos do programa relacionados com as interações entre as unidades, como, por exemplo, chamadas de subprogramas e seus parâmetros. Dados o alto custo de aplicação, inerente de critérios baseados em mutação, e pelas próprias características do conjunto de operadores de Mutação de Interface, torna-se necessário definirem-se abordagens para reduzir esse custo. Assim, foram estabelecidas maneiras de se parametrizar a aplicação dos operadores de mutação, definindo-se critérios de Mutação de Interface alternativos, estendendo-se abordagem sutilizadas no teste de mutação convencional como mutação restrita. A aplicação de um critério de teste está fortemente condicionada à sua automatização. A definição de um critério de teste sem que pelo menos se apontem soluções para sua automatização tem pouca utilidade prática. Por isso, especificou-se e implementou-se a ferramenta PROTEUM/IM para apoiar a aplicação do critério Mutação de Interface. Essa ferramenta torna-se essencial neste trabalho à medida que permite que estudos empíricos possam ser realizados, avaliando o critério proposto. Dois estudos de caso são apresentados. Esses estudos aplicam o critério Mutação de interface em programas reais e buscam avaliar seu custo e sua eficácia em revelar erros. Estes estudos aplicam ainda critérios alternativos, mostrando que a Mutação de interface é bastante efetiva em revelar erros o de ter custo de aplicação bastante reduzido, quando aplicada de maneira incremental, utilizando-se as parametrizações que os operadores de mutação oferecem. / The project of test cases is one of the most important topics in the software testing activity. Several criteria have been proposed aiming at allowing the evaluation and selection of test cases in a systematic and theoretically well founded way. Unfortunately, the use of most of these criteria is restricted to the unit testing phase. For other testing phases, in particular for integration testing. there is a lack of such criteria, mainly because the existing criteria define test requirements only in the scope of a single unit. They arc not able to effectively exercise the interactions between units, what should be the focus of integration testing. Excepting some few works that extend structural criteria to the interprocedural level, only functional testing has been used at integration testing phase. Given this lack of criteria and the complementary characteristics of different testing techniques, this thesis presents an interprocedural fault based criterion named Interface Mutation. This criterion exercises the interactions between units through the selection of test cases that distinguish mutants created by introducing typical faults that characterize integration errors. A set of Interface Mutation operators was defined. The focus of these operators are the points of the program related to the unit interactions, for instance, subprogram calls and their parameters. Given the high cost associated to mutation testing in general and particularly to the Interface Mutation operators, it is necessary to define some approaches to reduce its application cost. Thus, some parameterizations were defined to the mutation operators, allowing to establish alternative Interface Mutation criteria, extending approaches already used in conventional mutation testing, as random mutation and constrained mutation. The application of any testing criterion strongly depends on its automatization. The definition of a criterion, without pointing out ways to its implementation has little practical utility. So, a tool named PROTEUM/IM was specified and implemented to support the application of Interface Mutation. This tool is an essential point in the present work because it allows the conduction of empirical studies aiming at evaluating the proposed criterion. Two case studies arc presented. In these studies the criterion Interface Mutation is applied to real programs and the cost of its application as well as its errors revealing effectiveness are evaluated. Alternative criteria are also used. Showing that Interface Mutation is very effective to reveal errors and can be applied with a reduced cost if used in an incremental way, taking advantage of the parameterization characteristics provided by the Interface Mutation operators set.

Depuração é a atividade responsável pela localização e correção de defeitos gerados durante o desenvolvimento de programas. A depuração ocorre devido à atividade de teste bem-sucedida, na qual falhas no comportamento do programa são reveladas, indicando a existência de defeitos. Diversas técnicas têm sido propostas para automatizar a tarefa de depuração de programas. Algumas delas utilizam heurísticas baseadas em informações de cobertura obtidas da execução de testes. O objetivo é indicar trechos de código do programa mais suspeitos de conter defeitos. As informações de cobertura mais usadas em depuração automatizada são baseadas no teste estrutural de unidade. A cobertura de integração, obtida por meio da comunicação entre as unidades de um programa, pode trazer novas informações sobre o código executado, possibilitando a criação de novas estratégias para a tarefa de localização de defeitos. Este trabalho apresenta uma nova técnica de localização de defeitos chamada Depuração de programas baseada em Cobertura de Integração (DCI). São apresentadas duas coberturas de integração baseadas nas chamadas de métodos de um programa. Essas coberturas são usadas para a proposição de roteiros de busca dos defeitos a partir dos métodos considerados mais suspeitos. As informações de cobertura de unidade são então utilizadas para a localização dos defeitos dentro dos métodos. A DCI também utiliza uma nova heurística para atribuição de valores de suspeição a entidades de integração estática dos programas como pacotes, classes e métodos, fornecendo também um roteiro para a procura dos defeitos. Os experimentos realizados em programas reais mostram que a DCI permite realizar a localização de defeitos de forma mais eficaz do que o uso de informações de cobertura de unidade isoladamente. / Debugging is the activity responsible for localizing and fixing faults generated during software development. Debugging occurs due to a successful testing activity, in which failures in the behavior of the program are revealed, indicating the existence of faults. Several techniques have been proposed to automate the debugging tasks, especially the fault localization task. Some techniques use heuristics based on coverage data obtained from the execution of tests. The goal is to indicate program code excerpts more likely to contain faults. The coverage data mostly used in automated debugging is based on white-box unit testing. Integration coverage data, obtained from the communication between the units of a program, can bring about new information with respect to the executed code, which allows new strategies to the fault localization task to be devised. This work presents a new fault localization technique called Debugging based on Integration Coverage (DIC). Two integration coverages based on method invocations are presented. These coverages are used to propose two search strategies that provides a roadmap to locate faults by investigating the more suspicious methods. The unit coverage information are used to search the faulty statement inside the suspicious methods. The DIC technique also proposes a heuristic that assigns suspiciousness values to static integration entities of the programs, namely, packages, classes, and methods. This heuristic also provides a roadmap to search for the faults. Experiments using real programs show that DIC is more effective to locate faults than solely using unit coverage information.

No description available.

由於特徵尺寸不斷縮小，集成電路在生產過程中的工藝偏差在運行環境中溫度和電壓等參數的波動以及在使用過程中的老化等效應越來越嚴重，導致芯片的時序行為出現很大的不確定性。多數情況下，芯片的關鍵路徑會不時出現時序錯誤。加入更多的時序餘量不是一種很好的解決方案，因為這種保守的設計方法會抵消工藝進步帶來的性能上的好處。這就為設計一個時序可靠的系統提出了極大的挑戰，其中的一些關鍵問題包括：(一)如何有效地分配有限的功率預算去優化那些正爆炸式增加的關鍵路徑的時序性能；(二)如何產生能夠捕捉準確的最壞情況時延的高品質測試向量；(三)為了能夠取得更好的功耗和性能上的平衡，我們將不得不允許芯片在使用過程中出現一些頻率很低的時序錯誤。隨之而來的問題是如何做到在線的檢錯和糾錯。 / 為了解決上述問題，我們首先發明了一種新的技術用於識別所謂的虛假路徑，該方法使我們能夠發現比傳統方法更多的虛假路徑。當將所提取的虛假路徑集成到靜態時序分析工具里以後，我們可以得到更為準確的時序分析結果，同時也能節省本來用於優化這些路徑的成本。接著，考慮到現有的延時自動向量生成(ATPG) 方法會產生功能模式下無法出現的測試向量，這種向量可能會造成測試過程中在被激活的路徑周圍出現過多(或過少)的電源噪聲(PSN) ，從而導致測試過度或者測試不足情況。為此，我們提出了一種新的偽功能ATPG工具。通過同時考慮功能約束以及電路的物理佈局信息，我們使用類似ATPG 的算法產生狀態跳變使其能最大化已激活的路徑周圍的PSN影響。最後，基於近似電路的原理，我們提出了一種新的在線原位校正技術，即InTimeFix，用於糾正時序錯誤。由於實現近似電路的綜合僅需要簡單的電路結構分析，因此該技術能夠很容易的擴展到大型電路設計上去。 / With technology scaling, integrated circuits (ICs) suffer from increasing process, voltage, and temperature (PVT) variations and aging effects. In most cases, these reliability threats manifest themselves as timing errors on speed-paths (i.e., critical or near-critical paths) of the circuit. Embedding a large design guard band to prevent timing errors to occur is not an attractive solution, since this conservative design methodology diminishes the benefit of technology scaling. This creates several challenges on build a reliable systems, and the key problems include (i) how to optimize circuit’s timing performance with limited power budget for explosively increased potential speed-paths; (ii) how to generate high quality delay test pattern to capture ICs’ accurate worst-case delay; (iii) to have better power and performance tradeoff, we have to accept some infrequent timing errors in circuit’s the usage phase. Therefore, the question is how to achieve online timing error resilience. / To address the above issues, we first develop a novel technique to identify so-called false paths, which facilitate us to find much more false paths than conventional methods. By integrating our identified false paths into static timing analysis tool, we are able to achieve more accurate timing information and also save the cost used to optimize false paths. Then, due to the fact that existing delay automated test pattern generation (ATPG) methods may generate test patterns that are functionally-unreachable, and such patterns may incur excessive (or limited) power supply noise (PSN) on sensitized paths in test mode, thus leading to over-testing or under-testing of the circuits, we propose a novel pseudo-functional ATPG tool. By taking both circuit layout information and functional constrains into account, we use ATPG like algorithm to justify transitions that pose the maximized functional PSN effects on sensitized critical paths. Finally, we propose a novel in-situ correction technique to mask timing errors, namely InTimeFix, by introducing redundant approximation circuit with more timing slack for speed-paths into the design. The synthesis of the approximation circuit relies on simple structural analysis of the original circuit, which is easily scalable to large IC designs. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Yuan, Feng. / Thesis (Ph.D.)--Chinese University of Hong Kong, 2012. / Includes bibliographical references (leaves 88-100). / Abstract also in Chinese. / Abstract --- p.i / Acknowledgement --- p.iv / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Challenges to Solve Timing Uncertainty Problem --- p.2 / Chapter 1.2 --- Contributions and Thesis Outline --- p.5 / Chapter 2 --- Background --- p.7 / Chapter 2.1 --- Sources of Timing Uncertainty --- p.7 / Chapter 2.1.1 --- Process Variation --- p.7 / Chapter 2.1.2 --- Runtime Environment Fluctuation --- p.9 / Chapter 2.1.3 --- Aging Effect --- p.10 / Chapter 2.2 --- Technical Flow to Solve Timing Uncertainty Problem --- p.10 / Chapter 2.3 --- False Path --- p.12 / Chapter 2.3.1 --- Path Sensitization Criteria --- p.12 / Chapter 2.3.2 --- False Path Aware Timing Analysis --- p.13 / Chapter 2.4 --- Manufacturing Testing --- p.14 / Chapter 2.4.1 --- Functional Testing vs. Structural Testing --- p.14 / Chapter 2.4.2 --- Scan-Based DfT --- p.15 / Chapter 2.4.3 --- Pseudo-Functional Testing --- p.17 / Chapter 2.5 --- Timing Error Tolerance --- p.19 / Chapter 2.5.1 --- Timing Error Detection --- p.19 / Chapter 2.5.2 --- Timing Error Recover --- p.20 / Chapter 3 --- Timing-Independent False Path Identification --- p.23 / Chapter 3.1 --- Introduction --- p.23 / Chapter 3.2 --- Preliminaries and Motivation --- p.26 / Chapter 3.2.1 --- Motivation --- p.27 / Chapter 3.3 --- False Path Examination Considering Illegal States --- p.28 / Chapter 3.3.1 --- Path Sensitization Criterion --- p.28 / Chapter 3.3.2 --- Path-Aware Illegal State Identification --- p.30 / Chapter 3.3.3 --- Proposed Examination Procedure --- p.31 / Chapter 3.4 --- False Path Identification --- p.32 / Chapter 3.4.1 --- Overall Flow --- p.34 / Chapter 3.4.2 --- Static Implication Learning --- p.35 / Chapter 3.4.3 --- Suspicious Node Extraction --- p.36 / Chapter 3.4.4 --- S-Frontier Propagation --- p.37 / Chapter 3.5 --- Experimental Results --- p.38 / Chapter 3.6 --- Conclusion and Future Work --- p.42 / Chapter 4 --- PSN Aware Pseudo-Functional Delay Testing --- p.43 / Chapter 4.1 --- Introduction --- p.43 / Chapter 4.2 --- Preliminaries and Motivation --- p.45 / Chapter 4.2.1 --- Motivation --- p.46 / Chapter 4.3 --- Proposed Methodology --- p.48 / Chapter 4.4 --- Maximizing PSN Effects under Functional Constraints --- p.50 / Chapter 4.4.1 --- Pseudo-Functional Relevant Transitions Generation --- p.51 / Chapter 4.5 --- Experimental Results --- p.59 / Chapter 4.5.1 --- Experimental Setup --- p.59 / Chapter 4.5.2 --- Results and Discussion --- p.60 / Chapter 4.6 --- Conclusion --- p.64 / Chapter 5 --- In-Situ Timing Error Masking in Logic Circuits --- p.65 / Chapter 5.1 --- Introduction --- p.65 / Chapter 5.2 --- Prior Work and Motivation --- p.67 / Chapter 5.3 --- In-Situ Timing Error Masking with Approximate Logic --- p.69 / Chapter 5.3.1 --- Equivalent Circuit Construction with Approximate Logic --- p.70 / Chapter 5.3.2 --- Timing Error Masking with Approximate Logic --- p.72 / Chapter 5.4 --- Cost-Efficient Synthesis for InTimeFix --- p.75 / Chapter 5.4.1 --- Overall Flow --- p.76 / Chapter 5.4.2 --- Prime Critical Segment Extraction --- p.77 / Chapter 5.4.3 --- Prime Critical Segment Merging --- p.79 / Chapter 5.5 --- Experimental Results --- p.81 / Chapter 5.5.1 --- Experimental Setup --- p.81 / Chapter 5.5.2 --- Results and Discussion --- p.82 / Chapter 5.6 --- Conclusion --- p.85 / Chapter 6 --- Conclusion and Future Work --- p.86 / Bibliography --- p.100

Depuração é a atividade responsável pela localização e correção de defeitos gerados durante o desenvolvimento de programas. A depuração ocorre devido à atividade de teste bem-sucedida, na qual falhas no comportamento do programa são reveladas, indicando a existência de defeitos. Diversas técnicas têm sido propostas para automatizar a tarefa de depuração de programas. Algumas delas utilizam heurísticas baseadas em informações de cobertura obtidas da execução de testes. O objetivo é indicar trechos de código do programa mais suspeitos de conter defeitos. As informações de cobertura mais usadas em depuração automatizada são baseadas no teste estrutural de unidade. A cobertura de integração, obtida por meio da comunicação entre as unidades de um programa, pode trazer novas informações sobre o código executado, possibilitando a criação de novas estratégias para a tarefa de localização de defeitos. Este trabalho apresenta uma nova técnica de localização de defeitos chamada Depuração de programas baseada em Cobertura de Integração (DCI). São apresentadas duas coberturas de integração baseadas nas chamadas de métodos de um programa. Essas coberturas são usadas para a proposição de roteiros de busca dos defeitos a partir dos métodos considerados mais suspeitos. As informações de cobertura de unidade são então utilizadas para a localização dos defeitos dentro dos métodos. A DCI também utiliza uma nova heurística para atribuição de valores de suspeição a entidades de integração estática dos programas como pacotes, classes e métodos, fornecendo também um roteiro para a procura dos defeitos. Os experimentos realizados em programas reais mostram que a DCI permite realizar a localização de defeitos de forma mais eficaz do que o uso de informações de cobertura de unidade isoladamente. / Debugging is the activity responsible for localizing and fixing faults generated during software development. Debugging occurs due to a successful testing activity, in which failures in the behavior of the program are revealed, indicating the existence of faults. Several techniques have been proposed to automate the debugging tasks, especially the fault localization task. Some techniques use heuristics based on coverage data obtained from the execution of tests. The goal is to indicate program code excerpts more likely to contain faults. The coverage data mostly used in automated debugging is based on white-box unit testing. Integration coverage data, obtained from the communication between the units of a program, can bring about new information with respect to the executed code, which allows new strategies to the fault localization task to be devised. This work presents a new fault localization technique called Debugging based on Integration Coverage (DIC). Two integration coverages based on method invocations are presented. These coverages are used to propose two search strategies that provides a roadmap to locate faults by investigating the more suspicious methods. The unit coverage information are used to search the faulty statement inside the suspicious methods. The DIC technique also proposes a heuristic that assigns suspiciousness values to static integration entities of the programs, namely, packages, classes, and methods. This heuristic also provides a roadmap to search for the faults. Experiments using real programs show that DIC is more effective to locate faults than solely using unit coverage information.

<p>DUE TO COPYRIGHT-RESTRICTIONS THIS PAPER IS NOT AVAILABLE FOR DOWNLOAD!</p><p>The thesis describes a system which communicates in real time with data loggers. The system has been streamlined and integrated with existing application so that each user can get a graphical presentation in real time on what has been sent to and from the units. The user interface and communication has been designed to be robust, user friendly, secure and offer functionality that yields the users of the system added value. The system is flexible from the design perspective and is low maintenance.</p>

DUE TO COPYRIGHT-RESTRICTIONS THIS PAPER IS NOT AVAILABLE FOR DOWNLOAD! The thesis describes a system which communicates in real time with data loggers. The system has been streamlined and integrated with existing application so that each user can get a graphical presentation in real time on what has been sent to and from the units. The user interface and communication has been designed to be robust, user friendly, secure and offer functionality that yields the users of the system added value. The system is flexible from the design perspective and is low maintenance.

No description available.