No description available.

acase@tulane.edu

A novel algorithm for the simplified tele-operation of mobile-manipulator systems is presented. The algorithm allows for unified, intuitive, and coordinated control of mobile manipulators, systems comprised of a robotic arm mounted on a mobile base. Unlike other approaches, the mobile-manipulator system is modeled and controlled as two separate entities rather than as a whole. The algorithm consists of thee states. In the rst state a 6-DOF (degree-of-freedom) joystick is used to freely control the manipulator's position and orientation. The second state occurs when the manipulator approaches a singular configuration, a con guration where the arm instantaneously loses a DOF of motion capability. This state causes the mobile base to proceed in such a way as to keep the end-effector moving in its last direction of motion. This is done through the use of a constrained optimization routine. The third state is triggered by the user: once the end-effector is in the desired position, the mobile base and manipulator both move with respect to one another keeping the end-effector stationary and placing the manipulator into an ideal configuration. The proposed algorithm avoids the problems of algorithmic singularities and simplifies the control approach. The algorithm has been implemented on the Jasper Mobile-Manipulator System. Test results show that the developed algorithm is effective at moving the system in an intuitive manner.

Thesis (Ph. D.)--University of Texas at Austin, 2001. / Vita. Includes bibliographical references (leaves 1973-1092). Available also in a digital version from Dissertation Abstracts.

No description available.

No description available.

Thesis advisor: Carling Hay / Modern day climate change is exacerbating sea level change both locally and globally. The magnitudes of these changes are dependent on numerous global and regional factors that make it difficult to accurately project local sea level into the future. In Alaska, there are many processes contributing to sea level changes along the coast. In particular, there is substantial vertical land movement, in the form of uplift and subsidence, due to the isostatic adjustment of the land once burdened by ice sheets. In Northern Alaska, there is an additional source of land motion that occurs because the flat, tundra landscape is underlain by ~100-300m of permafrost. This permafrost is currently melting and the area is experiencing land subsidence because of it. This study refines sea level projections along northern Alaska by accounting for this extra climate signal. The addition of permafrost-melt induced isotropic land subsidence in projections for the northern coast of Alaska results in sea level rise estimates at the end of the century that double previously published projections. These improved Alaska projections will be vital for the coastal communities, especially in coming decades, in order to minimize losses of coastal property and infrastructure. / Thesis (BS) — Boston College, 2018. / Submitted to: Boston College. College of Arts and Sciences. / Discipline: Arts and Sciences Honors Program. / Discipline: Earth and Environmental Sciences.

No description available.

This thesis is concerned with the characteristics and development of scree slopes, as illustrated by examples from a small alpine valley. The major controls of scree slope development and processes are discussed with special emphasis on rockfalls and snow avalanches. The results of debris accumulation measurements on networks of cleaned boulders and polyethelene squares at seven screes from 1968-1972 are presented and discussed. The techniques are suggested as a valid means of measuring debris accumulation by avalanches. The surface sedimentary characteristics of five screes are examined in detail with particular emphasis on size sorting at various levels over the scree and possible relationships between sedimentary characteristics and sorting. Detail of the profile form of these screes is also given and the avalanche modification of screes discussed. / Thesis / Doctor of Philosophy (PhD)

Application Specific Integrated Circuits (ASIC) and Field Programmable Gate Arrays (FPGA) verification is quite a time consuming phase in design flow cycle and it can be done using methodologies such as Universal Verification Methodology (UVM) and formal verification.The UVM methodology is simulation based verification where in the verifier will have to trigger the Design Under Test (DUT) manually by writing sequences which target different features of the DUT and the verification environment can also have verification directives such as assertions to spot design bugs. Formal verification on the other hand is purely assertion based verification where we describe the expected DUT behaviour using System Verilog Assertion (SVA) and we check for design sanity by exercising the assertions by letting the formal tool drive the inputs to the design in a constrained way. This completely eliminates the need of having to define sequences to drive the inputs. This thesis will bring up formal verification using jasper gold to light and will help verifiers to decide on how much of formal verification methodology can be used in verification of an IP with respect to the complexity of the design and the design behaviour to be verified. The results from this thesis proves how efficient formal verification was with respect to simulation based verification, to stress the design to test for corner case behaviour. The reason why formal verification cannot be extended for Top-Level Verification (TLV) and end to end functional verification is because of design complexity and this was also explored with the help of a complex ethernet design. Finally, a guideline as to when to use simulation based verification and formal verification was formulated. / ASIC och FPGA verifiering är en största del och är en tidskrävande fas av desingflödescyckeln. Det kan man göra den genom UVM eller Formell verifiering metoder.UVM metoder är simulering baserad verifiering där verifieraren måste utlösa DUT genom att skriva sekvenser som rikta olika funktioner av DUT och verifiering miljöer kan också ha verifiering direktiv som assertions som kan upptäcka designbugs.Formal verifiering är en assertion baserad verifiering metoder där i man kan beskriva förväntad DUT uppträdandet genom system verilog assertions (SVA) och verifiera designen genom använder assertions genom att låta det formal driva ingångarna till designen på ett begränsat sätt.Detta eliminerar helt behovet av att behöva definiera sekvenser för att driva ingångarna. Denna examensarbetena kommer att beskriva om formell verifiering med jasper gold och kommer att hjälpa verifierar bestämma hur mycket av den formal verifiering metoden kan man användas för att verifiera en ASIC IP med avseende på komplexitet och design uppträdandet att vara verifierat. Resultaten från denna examensarbetena kommer att bevisa hur effektiv formell metoderna var med avseende på simulering metoder att stressa design och verifiera den för undantags fall.Den ändleding varför formell verifiering metoder kan inte användande för TLV och från början till slut funktion verifiering är på grund av design komplexitet.Detta har analyserats med hjälp av en komplex ethernet design.En riktlinje för när kan man använda simulering metoder och formal metoder var föreslagit.