<p>In Black-Scholes model, the parameters -a volatility and an interest rate were assumed as constants. In this thesis we concentrate on behaviour of the volatility as</p><p>a function and we find more realistic models for the volatility, which elimate a risk</p><p>connected with behaviour of the volatility of an underlying asset. That is</p><p>the reason why we will study the Uncertain Volatility Model. In Chapter</p><p>1 we will make some theoretical introduction to the Uncertain Volatility Model</p><p>introduced by Avellaneda, Levy and Paras and study how it behaves in the different scenarios. In</p><p>Chapter 2 we choose one of the scenarios. We also introduce the BSB equation</p><p>and try to make some modification to narrow the uncertainty bands using</p><p>the idea of a static hedging. In Chapter 3 we try to construct the proper</p><p>portfolio for the static hedging and compare the theoretical results with the real</p><p>market data from the Stockholm Stock Exchange.</p>

In Black-Scholes model, the parameters -a volatility and an interest rate were assumed as constants. In this thesis we concentrate on behaviour of the volatility as a function and we find more realistic models for the volatility, which elimate a risk connected with behaviour of the volatility of an underlying asset. That is the reason why we will study the Uncertain Volatility Model. In Chapter 1 we will make some theoretical introduction to the Uncertain Volatility Model introduced by Avellaneda, Levy and Paras and study how it behaves in the different scenarios. In Chapter 2 we choose one of the scenarios. We also introduce the BSB equation and try to make some modification to narrow the uncertainty bands using the idea of a static hedging. In Chapter 3 we try to construct the proper portfolio for the static hedging and compare the theoretical results with the real market data from the Stockholm Stock Exchange.

The topic of the master´s thesis is to verify Acquisition Engine and Tracking Engine in the Microcore GNSS Baseband digital circuit from Honeywell. Theoretical part contains a brief introduction into the satellite position determination, basic principles of the verified blocks is given and UVM methodology is introduced. Practical part contains requirements, test cases and test procedures. The verification environment is also described. In the last part of the thesis is the verification process and it´s results.

Application Specific Integrated Circuits (ASIC) and Field Programmable Gate Arrays (FPGA) verification is quite a time consuming phase in design flow cycle and it can be done using methodologies such as Universal Verification Methodology (UVM) and formal verification.The UVM methodology is simulation based verification where in the verifier will have to trigger the Design Under Test (DUT) manually by writing sequences which target different features of the DUT and the verification environment can also have verification directives such as assertions to spot design bugs. Formal verification on the other hand is purely assertion based verification where we describe the expected DUT behaviour using System Verilog Assertion (SVA) and we check for design sanity by exercising the assertions by letting the formal tool drive the inputs to the design in a constrained way. This completely eliminates the need of having to define sequences to drive the inputs. This thesis will bring up formal verification using jasper gold to light and will help verifiers to decide on how much of formal verification methodology can be used in verification of an IP with respect to the complexity of the design and the design behaviour to be verified. The results from this thesis proves how efficient formal verification was with respect to simulation based verification, to stress the design to test for corner case behaviour. The reason why formal verification cannot be extended for Top-Level Verification (TLV) and end to end functional verification is because of design complexity and this was also explored with the help of a complex ethernet design. Finally, a guideline as to when to use simulation based verification and formal verification was formulated. / ASIC och FPGA verifiering är en största del och är en tidskrävande fas av desingflödescyckeln. Det kan man göra den genom UVM eller Formell verifiering metoder.UVM metoder är simulering baserad verifiering där verifieraren måste utlösa DUT genom att skriva sekvenser som rikta olika funktioner av DUT och verifiering miljöer kan också ha verifiering direktiv som assertions som kan upptäcka designbugs.Formal verifiering är en assertion baserad verifiering metoder där i man kan beskriva förväntad DUT uppträdandet genom system verilog assertions (SVA) och verifiera designen genom använder assertions genom att låta det formal driva ingångarna till designen på ett begränsat sätt.Detta eliminerar helt behovet av att behöva definiera sekvenser för att driva ingångarna. Denna examensarbetena kommer att beskriva om formell verifiering med jasper gold och kommer att hjälpa verifierar bestämma hur mycket av den formal verifiering metoden kan man användas för att verifiera en ASIC IP med avseende på komplexitet och design uppträdandet att vara verifierat. Resultaten från denna examensarbetena kommer att bevisa hur effektiv formell metoderna var med avseende på simulering metoder att stressa design och verifiera den för undantags fall.Den ändleding varför formell verifiering metoder kan inte användande för TLV och från början till slut funktion verifiering är på grund av design komplexitet.Detta har analyserats med hjälp av en komplex ethernet design.En riktlinje för när kan man använda simulering metoder och formal metoder var föreslagit.

Submitted by Marlucy Farias Medeiros (marlucy.farias@unipampa.edu.br) on 2018-05-11T18:34:32Z No. of bitstreams: 1 Vinícius Bittencourt da Silva- 2018.pdf: 4217704 bytes, checksum: 062fdfd3aa89f2dbd2679f836c3bad2d (MD5) / Approved for entry into archive by Dayse Pestana (dayse.pestana@unipampa.edu.br) on 2018-05-14T11:58:52Z (GMT) No. of bitstreams: 1 Vinícius Bittencourt da Silva- 2018.pdf: 4217704 bytes, checksum: 062fdfd3aa89f2dbd2679f836c3bad2d (MD5) / Made available in DSpace on 2018-05-14T11:58:52Z (GMT). No. of bitstreams: 1 Vinícius Bittencourt da Silva- 2018.pdf: 4217704 bytes, checksum: 062fdfd3aa89f2dbd2679f836c3bad2d (MD5) Previous issue date: 2018-02-07 / Atualmente, o tempo de inserção de um produto de hardware no mercado é cada vez menor apesar do crescimento de sua complexidade. Portanto, é importante que o processo de construção seja cada vez mais rápido. Entre as medidas para ganhar desempenho a otimização do tempo despendido em verificação é fundamental, pois cerca de 70% do tempo de projeto é aplicado nessa atividade. Esse processo inicia-se juntamente com o desenvolvimento, pois, caso seja detectado um erro somente no estágio final de desenvolvimento é possível que haja atrasos para cumprir os prazos de entrega. Nesse sentido, este trabalho apresenta a USAG, uma ferramenta semi-automática desenvolvida para construir ambientes de verificação usando a metodologia UVM (a qual é a metodologia padrão atualmente) aplicada ao projeto de circuitos integrados escritos em SystemVerilog. Esta ferramenta vem para ajudar no processo de verificação de hardware acelerando a criação do ambiente de verificação, uma vez que ele gera as estruturas e interconexões da metodologia e produz os arquivos para simulação. Qualquer ferramenta que suporte SystemVerilog juntamente com a Metodologia UVM pode executar o ambiente de verificação gerado pela USAG. Além disso, a ferramenta é baseada na Web para ser acessível a partir de qualquer local sem a necessidade de um sistema operacional específico ou configuração para usá-la. Finalmente, são apresentados os resultados de ambientes de verificação UVM obtidos a partir da entrada de códigos fonte em SystemVerilog na USAG. A partir dos resultados obtidos e da análise da utilização por parte de testadores conclui-se que a USAG é eficaz no que tange os objetivos propostos. / Currently, the insertion time of a hardware pro ducts in the market is decreasing despite the growth of its complexity. Therefore, it is important that the construction process is getting faster and faster. Among the ways to gain performance, the optimization of the time spent in verification is fundamental, because ab out 70% of the project time is applied in this activity. This process starts with the development, because if an error is detected only in the final stage of development, there may be delays to comply with delivery times. In this way, this work presents USAG, a semi-automatic tool developed to construct verification environments using the UVM methodology (which is the current standard methodology) applied to the design of integrated circuits written in SystemVerilog. This tool comes to assist in the hardware verification process by accelerating the creation of the verification environment as it generates the structures and interconnections of the methodology and produces the files for simulation. Any tool that supports SystemVerilog together with the UVM Methodology can execute the verification environment generated by the USAG. In addition, the tool is web-based to be accessible from any lo cation without the need for a specific operating system or configuration to use it. Finally, the results of UVM verification environments obtained from the entry of source co des in SystemVerilog in USAG are presented.

One of the currently most used approaches for verification of hardware systems is functional verification. This master thesis describes design and implementation of a verification environment using UVM (Universal Verification Methodology) methodology for verifying the correctness of the robot controller in order to eliminate functional errors and faults of its implementation. The theoretical part of the thesis describes the basic information about functional verification, methodologies for creating verification environments, the SystemVerilog language and fault tolerance methodologies. The next part of thesis focuses on the design of the verification environment, its implementation and the creation of tests used to verify the correctness of the robot controller. Results of verification are discussed and evaluated in the conclusion of this work.

According to the International Roadmap for semiconductors (ITRS), there should be a 1000X improvement in performance with only 120% increase in the power budget and no increase in the design team size to deal with designs that are 10X more complex. One solution to cope with this complexity is to increase the granularity of the building blocks for developing new architectures. As a solution, Dynamically Reconfigurable Resource Array (DRRA) with Distributed Memory Architecture(DiMArch) was developed. As the design complexity increased, the need for verification became inevitable in the design flow. To include the feature of reusability, a reconfigurable verification environment is required to effectively verify the device under test (DUT) and also improve the productivity in the design cycle. The thesis work begins with the specification &amp; design and also the verification plans for the DRRA and DiMArch. The major task of the thesis work is in developing a reconfigurable verification environment for the DRRA using Universal Verification Methodology (UVM) and a systemlevel verification test bench for the DiMArch . This thesis work also focuses on the possible power optimization in the design.

This master thesis deals with application of an evolutionary algorithm in the creation of regression tests. In the first section, description of functional verification, verification methodology, regression tests and evolutionary algorithms is provided. In the following section, the evolutionary algorithm, the purpose of which is to achieve reduction of the number of test vectors obtained in the process of functional verification, is proposed. Afterwards, the proposed algorithm is implemented and a set of experiments is evaluated. The results are discussed.

This thesis focuses on the automation of scenarios creation for Portable Stimulus standard. The main goal of the work is an automatic generation of tests, which are defined as graphs for the Questa inFact tool from the Mentor company. For the automation I used an evolutionary algorithm with using a grammatical evolution.  The generated scenarios are connected to the existing verification environment based on UVM methodology, then the verification of the connected component is started. Based on the achieved functional and structural coverage, the individual's fitness value is calculated and propagated into an evolutionary algorithm.  At the end of the work, experiments are performed on the timer component and the contribution of the proposed evolutionary algorithm is evaluated. The proposed evolutionary algorithm is configurable by  grammar and user-defined basic transactions, which allows a wide range of uses. The evolutionary algorithm managed to achieve high functional and structural coverage on the verified timer component.

The goal of this thesis is to analyze and to find solutions of optimization problems derived from automation of functional verification of hardware using artificial neural networks. Verification of any integrated circuit (so called Design Under Verification, DUV) using technique called coverage-driven verification and universal verification methodology (UVM) is carried out by sending stimuli inputs into DUV. The verification environment continuously monitors percentual coverage of DUV functionality given by the specification. In current context, coverage stands for measurable property of DUV, like count of verified arithemtic operations or count of executed lines of code. Based on the final coverage, it is possible to determine whether the coverage of DUV is high enough to declare DUV as verified. Otherwise, the input stimuli set needs to change in order to achieve higher coverage. Current trend is to generate this set by technique called constrained-random stimulus generation. We will practice this technique by using pseudorandom program generator (PNG). In this paper, we propose multiple solutions for following two optimization problems. First problem is ongoing modification of PNG constraints in such a way that the DUV can be verified by generated stimuli as quickly as possible. Second one is the problem of seeking the smallest set of stimuli such that this set verifies DUV. The qualities of the proposed solutions are verified on 32-bit application-specific instruction set processors (ASIPs) called Codasip uRISC and Codix Cobalt.