Within the neoliberal context of today’s urbanism, a growing number of inner-city megaprojects aim to transform brownfield sites—accompanied by gentrification and tourism. However, there is no systematic review exploring the interplay between these phenomena. This paper aims to systemize the existing scientific contributions by means of a literature review. Using different databases, a total number of 797 scientific documents have been identified. After several screening steps, a final set of 66 studies was included in the review. I present an analysis from a quantitative and a qualitative perspective, exploring bibliometric aspects, concepts, methods, and relevant lines of discussion. The area studied is a relatively young and emerging field. Within the discussion, there is a strong dominance of countries located in the global north, with Spain, the UK, and the U.S. at the forefront. From a methodological point of view, qualitative and mixed methods are mostly applied. The discussion of megaprojects, gentrification, and tourism has an important descriptive focus, with main topics such as planning, justice, and motivations. There are considerable conceptual deficits, as one-quarter of the studies do not clearly explain their methods. Future research needs to find ways to enable knowledge transfer to planning practice.

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As the speed of operation of VLSI devices has increased, delay fault testing has become a more important factor in VLSI testing. Due to the large number of gates in a VLSI circuit, the gate level test generation methodologies may become infeasible for delay test generation. In this work, a new behavioral delay fault model that aims at simplifying the delay test generation problem for digital circuits is presented. The model is defined using VHDL. It is shown that each defined behavioral level delay fault can be mapped to a gate level equivalent fault and/or physical failure. A systematic way of representing a behavioral model in terms of a data flow graph is presented. A behavioral level input-output path is defined and a strategy to generate tests for delay faults along a behavioral path is presented. It is then shown that tests developed from the behavioral model can test a gate level equivalent circuit for path delay faults. / Master of Science

In this thesis, several techniques for the test generation of VHDL behavioral models are proposed. An algorithm called HBTG, Hierarchical Behavioral Test Generator, is developed and implemented to systematically generate tests for VHDL behavioral models. HBTG accepts the Process Model Graph and the precomputed tests for the individual processes of the model from which it constructs a test sequence that exercises the model hierarchically. The construction of the test sequence is automatic if the tests for the individual processes of the model are provided. The test sequence derived can be used for the simulation of the model. By comparing the simulation outputs with the data sheet or the design specifications of the corresponding circuit, a user can tell if the functionality of the model is as expected or any functional faults exist. Simulation results and conclusions are given. Some suggestions for further improvements of the program are discussed. / Master of Science

This thesis describes the development of BACKANN, a tool for the back annotation of timing delays into VHDL models. BACKANN uses the Process Model Graph and the VHDL behavioral model generated by the Modeler's Assistant as the base for backannotation. BACKANN determines the delay values that are required for the signal assignments in the behavioral model. It generates a gate-level design of the model using the Synopsys Design Compiler. It extracts the values for the delays required from the gate-level design. It then back-annotates these values into the VHDL behavioral model. BACKANN is thus a design automation tool that helps the development of VHDL behavioral models with realistic timing and thus quickens the design cycle. / Master of Science

The author begins with a short introduction to current neural network practices and pitfalls including an in depth discussion of the meaning behind the equations. Specifically, a description of the underlying processes involved is given which likens training to the biological process of cell differentiation. Building on these ideas, an improved method of generating integer based binary neural networks is developed. This type of network is particularly useful for the optical character recognition problem, but methods for usage in the more general case are discussed. The new method does not use training as such. Rather, the training data is analyzed to determine the statistically significant relationships therein. These relationships are used to generate a neural network structure that is an idealization of the trained version in that it can accurately extrapolate from existing knowledge by exploiting known relationships in the training data. The paper then turns to the design and testing of a VLSI CMOS chip which was created to utilize the new technique. The chip is based on the MOSIS 2Jlm process using a 2200A x 2200A die that was shaped into a special purpose microprocessor that could be used in any of a number of pattern recognition applications with low power requirements and/or limiting considerations. Simulation results of the methods are then given in which it is shown that error rates of less than 5% for inputs containing up to 30% noise can easily be achieved. Finally, the thesis concludes with ideas on how the various methods described might be improved further. / Master of Science

This thesis describes the development of the Process Test Generation (PTG) software for the testing of single-process VHDL behavioral models. The PTG software, along with Hierarchical Behavioral Test Generator (HBTG) and Modeler's Assistant, forms a part of the Automatic Test Generation System being developed at Virginia Tech. The PTG software transforms the VHDL description of a circuit, given by Modeler's Assistant, into a Control Flow Graph (CFG) that describes the control and data flow information in the behavioral model. The process test generation algorithm, called the PTG algorithm, uses the CFG to generate stimulus/response test sets that test all the functions of the VHDL model. The algorithm creates events on signals, propagates these events and uses simulation to obtain responses. Various features present in the software like the generation of the Control Flow Graph, the PTG algorithm, and the construction of paths through the CFG to propagate and justify events, are discussed. The test sets generated by PTG can be used for the hierarchical test generation by HBTG, which was developed earlier. Another program, called Test Bench Generator (TBG), is presented in this thesis. It is used to convert the test sequence generated by HBTG into a VHDL Test Bench that can be used for simulation. / Master of Science