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Techn. Universiẗat, Diss., 2003--Berlin.

Ingeniero Civil Electricista / Los circuitos digitales, que juegan un papel crucial en la vida cotidiana, consumen grandes cantidades de potencia lo que es considerado como una situación no deseada, lo que es particularmente cierto para equipos que dependen de baterías como celulares, es por esto que los diseñadores de circuitos así como las herramientas de síntesis utilizan diferentes técnicas con el fin de reducir su consumo de potencia. Una de las técnicas de reducción de potencia mas exitosas es clock-gating cuyo objetivo es reducir el consumo de potencia generado por las transiciones debidas a la señal de clk. La reducción de potencia se logra mediante la inserción de clock-gating cells (celdas de clock-gating) que impiden que la señal de clk llegue a los Flip-Flop cuando el valor de la salida de estos no se espera que cambie. Los diseños basados en Latch, que si bien no son tan utilizados como los diseños basados en Flip-Flop debido a sus complejidades adicionales, todavía son utilizados gracias a ciertos beneficios que presentan las restricciones de timing (timing o sincronización) de los Latch, sin embargo ninguna de las herramientas de síntesis existentes permite la inserción automática de clock-gates para diseños basados en Latches, por lo que los diseñadores de circuitos se ven forzados a insertar las clock-gates de forma manual lo que es ineficiente. El presente trabajo se enfoca en los mecanismos de clock-gating y los requisitos que se deben cumplir para permitir su uso en diseños basados en Latches desde la perspectiva de una herramienta de síntesis, al tiempo que provee de una discusión teórica sobre las diferencias entre Latches y Flip-Flops y como estas diferencias fuerzan los requerimientos de una herramienta de inserción de clock-gates Considerando las restricciones que debieran aplicar para una herramienta de inserción de clock-gates automática enfocada en Latches y utilizando el entorno de desarrollo provisto por Synopsys así como el código existente en la herramienta de síntesis desarrollada por ellos, se desarrolla un prototipo de inserción de clock-gates para Latches como parte de Design-Compiler El prototipo una vez embebido en Design-Compiler es probado en diversos diseños creados con este propósito y un diseño de mayor envergadura provisto por uno de los clientes de Synopsys y que es utilizado durante el desarrollo de circuitos reales, lo cual permite verificar la robustez de la herramienta desarrollada en diseños grandes.

Growing main memory capacities and an increasing number of hardware threads in modern server systems led to fundamental changes in database architectures. Most importantly, query processing is nowadays performed on data that is often completely stored in main memory. Despite of a high main memory scan performance, index structures are still important components, but they have to be designed from scratch to cope with the specific characteristics of main memory and to exploit the high degree of parallelism. Current research mainly focused on adapting block-optimized B+-Trees, but these data structures were designed for secondary memory and involve comprehensive structural maintenance for updates. In this paper, we present the KISS-Tree, a latch-free in-memory index that is optimized for a minimum number of memory accesses and a high number of concurrent updates. More specifically, we aim for the same performance as modern hash-based algorithms but keeping the order-preserving nature of trees. We achieve this by using a prefix tree that incorporates virtual memory management functionality and compression schemes. In our experiments, we evaluate the KISS-Tree on different workloads and hardware platforms and compare the results to existing in-memory indexes. The KISS-Tree offers the highest reported read performance on current architectures, a balanced read/write performance, and has a low memory footprint.

<p>The aim of this work is to characterize the beam of the 60Co therapy unit “Siemens Gammatron 1”, used at the Swedish Radiation Protection Authority (SSI) to calibrate therapy level ionization chambers. SSI wants to know the spectra in the laboratory’s reference points and a verified, virtual model of the 60Co unit to be able to compare current and future experiments to Monte Carlo simulations.</p><p>EGSnrc is a code for performing Monte Carlo simulations. By using BEAMnrc, which is an additional package that simplifies the building process of a geometry in the EGS-code, the whole Gammatron at SSI was defined virtually. In this work virtual models for two experimental setups were built: the Gammatron irradiating in air to simulate the air-kerma calibration geometry and the Gammatron irradiating a water phantom similar to that used for the absorbed dose to water calibrations.</p><p>The simulations are divided into two different substeps: one for the fixed part of the Gammatron and one for the variable part to be able to study different entities and to shorten simulation times.</p><p>The virtual geometries are verified by comparing Monte Carlo results with measurements. When it was verified that the virtual geometries were to be trusted, they were used to generate the Gammatron photon spectra in air and water with different field sizes and at different depths. The contributions to the photon spectra from different regions in the Gammatron were also collected. This is something that is easy to achieve with Monte Carlo calculations, but difficult to obtain with ordinary detectors in real life measurements.</p><p>The results from this work give SSI knowledge of the photon spectra in their reference points for calibrations in air and in water phantom. The first step of the virtual model (fixed part of Gammatron) can be used for future experimental setups at SSI.</p>

The aim of this work is to characterize the beam of the 60Co therapy unit “Siemens Gammatron 1”, used at the Swedish Radiation Protection Authority (SSI) to calibrate therapy level ionization chambers. SSI wants to know the spectra in the laboratory’s reference points and a verified, virtual model of the 60Co unit to be able to compare current and future experiments to Monte Carlo simulations. EGSnrc is a code for performing Monte Carlo simulations. By using BEAMnrc, which is an additional package that simplifies the building process of a geometry in the EGS-code, the whole Gammatron at SSI was defined virtually. In this work virtual models for two experimental setups were built: the Gammatron irradiating in air to simulate the air-kerma calibration geometry and the Gammatron irradiating a water phantom similar to that used for the absorbed dose to water calibrations. The simulations are divided into two different substeps: one for the fixed part of the Gammatron and one for the variable part to be able to study different entities and to shorten simulation times. The virtual geometries are verified by comparing Monte Carlo results with measurements. When it was verified that the virtual geometries were to be trusted, they were used to generate the Gammatron photon spectra in air and water with different field sizes and at different depths. The contributions to the photon spectra from different regions in the Gammatron were also collected. This is something that is easy to achieve with Monte Carlo calculations, but difficult to obtain with ordinary detectors in real life measurements. The results from this work give SSI knowledge of the photon spectra in their reference points for calibrations in air and in water phantom. The first step of the virtual model (fixed part of Gammatron) can be used for future experimental setups at SSI.

Growing main memory capacities and an increasing number of hardware threads in modern server systems led to fundamental changes in database architectures. Most importantly, query processing is nowadays performed on data that is often completely stored in main memory. Despite of a high main memory scan performance, index structures are still important components, but they have to be designed from scratch to cope with the specific characteristics of main memory and to exploit the high degree of parallelism. Current research mainly focused on adapting block-optimized B+-Trees, but these data structures were designed for secondary memory and involve comprehensive structural maintenance for updates. In this paper, we present the KISS-Tree, a latch-free inmemory index that is optimized for a minimum number of memory accesses and a high number of concurrent updates. More specifically, we aim for the same performance as modern hash-based algorithms but keeping the order-preserving nature of trees. We achieve this by using a prefix tree that incorporates virtual memory management functionality and compression schemes. In our experiments, we evaluate the KISS-Tree on different workloads and hardware platforms and compare the results to existing in-memory indexes. The KISS-Tree offers the highest reported read performance on current architectures, a balanced read/write performance, and has a low memory footprint.

In recent years, due to advances in semiconductor technology and mature integrated circuit design, complex signal processing equipment is beginning to be replaced by the integrated circuit. This paper presents an integrated circuit programmable frequency generator for open-loop resonator application and its evaluation. It can eventually replace the conventional discrete component system and be used to find the resonance frequency shift for the readout of micro-balances or similar devices. The oscillator provides an analog tuning input to set the coarse center frequency and bit resolution, and uses a digital input to control the frequency sweep. Calculating the resonance frequency difference between the active balance and a passive reference can mitigate some environmental effects on the resonator (e.g. temperature). The generator circuit is designed using Synopsys¡¦ HSPICE and Cadence's Spectre to perform circuit simulation. The circuit is implemented by Taiwan Semiconductor Manufacturing Company in 0.35 £gm 2-poly 4-metal CMOS process technology. The potential detection precision of a micro-balance using the forward generator is assessed by connecting test chips to an evaluation PCB with commercial piezo crystals providing a known resonance frequency for testing. National Instruments¡¦ LABVIEW is used to record the data output, and MATLAB to analyze the results. A minimum detection accuracy of 1 kHz is demonstrated with this setup.

Due to technology scaling, the probability of a high energy radiation particle striking multiple transistors has continued to increase. This, in turn has created a need for new circuit designs that can tolerate multiple simultaneous errors. A common type of error in memory elements is the double node upset (DNU) which has continued to become more common. All existing DNU tolerant designs either suffer from high area and performance overhead, may lose the data stored in the element during clock gating due to high impedance states or are vulnerable to an error after a DNU occurs. In this dissertation, a novel latch design is proposed in which all nodes are capable of fully recovering their correct value after a single or double node upset, referred to as DNU robust. The proposed latch offers lower delay, power consumption and area requirements compared to existing DNU robust designs. Multiple simultaneous radiation induced errors are a current problem that must be studied in combinational logic. Typically, simulators are used early in the design phase which use netlists and rudimentary information of the process parameters to determine the error rate of a circuit. Existing simulators are able to accurately determine the effects when the problem space is limited to one error. However, existing methods do not provide accurate information when multiple concurrent errors occur due to inaccurate approximation of the glitch shape when multiple errors meet at a gate. To improve existing error simulation, a novel analytical methodology to determine the pulse shape when multiple simultaneous errors occur is proposed. Through extensive simulations, it is shown that the proposed methodology matches closely with HSPICE while providing a speedup of 15X. The analysis of the soft error rate of a circuit has continued to be a difficult problem due to the calculation of the logical effect on a pulse generated by a radiation particle. Common existing methods to determine logical effects use either exhaustive input pattern simulation or binary decision diagrams. The problem with both approaches is that simulation of the circuit can be intractably time consuming or can encounter memory blowup. To solve this issue, a simulation tool is proposed which employs partitioning to reduce the execution time and memory overhead. In addition, the tool integrates an accurate electrical masking model. Compared to existing simulation tools, the proposed tool can simulate circuits up to 90X faster.

Thesis evaluaes production of the body latch, which is used for window, window shutter and door locking. It is made from 11 375 steel sheet which is 1 mm thick. Annual production is 50000 pcs. Progresive cutting and drawing in one combined tool and finishing product in single opperation drawing tool was choosen as most effective. Single operation drawing will be operated manually. Tools was designed by series of technological callculations to which was projected presses Šmeral LDC 160 with additional devices. Acording to economic valuation, cost of production of one piece is 16,50 Kč and production becames profitable after production of 27185 pieces.