There is a lack of technology that facilitates knowledge sharing in the medical sector. In several countries there is a shortage of medical staff with the proper education to take care of patients suffering from dementia. However, modern mobile and web technology pave the way for new online knowledge sharing platforms which could help remedy this problem. This study investigates how an interface of a mobile e-library, aimed at sharing dementia-related knowledge, could be created. It also examines how care workers perceive it and if they could be willing to adopt the technology in the future. This thesis project was carried out at Svenskt Demenscentrum, a non-profit organization with the purpose of disseminating and collecting knowledge concerning dementia. The prototype was designed using the double diamond process. This included an initial literature study and state-of-the-art analysis, which was followed by two workshops with professional care workers. The final design was created iteratively with feedback from a focus group. A total of four sessions with the focus group were organized. The final prototype was evaluated using the Technology Acceptance Model (TAM) model. 12 participants took part in the user tests, all had previously taken care of patients suffering from dementia. The findings of the user tests suggest that the users perceived the interface as both useful and easy to use. This finding also indicates that the users, according to the TAM model, would be willing to adopt the technology if fully developed. All of the participants found the application fitting for smartphone devices. Some suggestions regarding further implementations of the interface included the addition of an onboarding process for those less familiar with modern design conventions and the inclusion of a social forum or discussion page that would allow for a direct knowledge exchange between the users. / Det finns en brist på teknologier som förenklar kunskapsdelning inom den medicinska sektorn. I flera länder har det dokumenterats en tilltagande brist vårdpersonal med tillräcklig utbildning för att ta hand om patienter som lider av demens. Kunskapsdelning kan underlättas med mobila onlineplattformar, utvecklade for att användare ska kunna dela expertis med varandra. Den här studien undersöker hur gränssnittet till ett mobilt e-bibliotek, med mal att dela demensrelaterade kunskaper, skulle kunna utvecklas. Den undersöker även om vårdpersonal och släktingar till demenssjuka kan förväntas anamma teknologin i framtiden. Detta masterarbete utfördes i samarbete med Svenskt Demenscentrum, en stiftelse som arbetar för att samla, strukturera och sprida kunskap om demens.  En prototyp for gränssnittet designades efter 'double Diamond'-modellen. Detta inkluderade genomförandet av en litteraturstudie, en 'state-of-the-art'-analys samt två workshops med professionell vårdpersonal. Den slutgiltiga designen togs fram iterativt med feedback från en fokusgrupp. Totalt organiserades fyra sessioner med fokusgruppen.  Den slutgiltiga prototypen utvärderades sedan efter 'Technology Acceptance'-modellen (TAM). Tolv deltagare rekryterades till användartesterna, alla med tidigare erfarenhet av demensvård, som vårdarbete eller släktingar. Resultatet från testerna antydde att användarna uppfattade prototypgranssnittet som både användbart och lättanvänt. I enlighet men TAM-modellen, implicerar detta att målgruppen är mottaglig för att använda en full implementation av teknologin. Alla deltagare uppfattade även prototypen som lämplig för 'smartphone'-enheter. Testdeltagarna lyfte även fram ett antal rekommendationer gällande vidareutvecklingen av gränssnittet. Bland annat föreslogs det att en 'onboarding'-process skulle kunna implementeras samt en diskussionssida; eller dylikt som skulle tillåta användarna att delta i ett direkt kunskapsutbyte med varandra.

Projeto baseado em células-padrão é a abordagem mais aplicada no mercado de ASIC atualmente. Essa abordagem de projeto consiste no reuso de bibliotecas de células pré-customizadas para gerar sistemas digitais mais complexos. Portanto a eficiência de um projeto ASIC está relacionado com a biblioteca em uso. A utilização de portas lógicas CMOS geradas automaticamente no fluxo de projeto de circuito integrado baseado em células-padrão representa uma perspectiva atraente para melhorar a qualidade de projeto ASIC. Essas células geradas por software são os elementos-chave dessa nova abordagem de mapeamento tecnológico livre de biblioteca, já proposto na literatura e agora adotado pela indústria. O mapeamento tecnológico livre de biblioteca, baseado na criação de células sob demanda, por software, gera flexibilidade aos projetistas de circuitos integrados, fornecendo ajuste otimizado em aplicações específicas. Contudo, tal abordagem representa um fluxo de projeto de circuito integrado baseado em células lógicas criadas sob demanda por software, as quais não são previamente validadas em silício até que o ASIC alvo seja prototipado. Neste trabalho, um circuito de teste específico é proposto para validar a funcionalidade completa de um conjunto de células lógicas, bem como verificar comportamentos de atraso e consumo, os quais podem ser correlacionados com as estimativas de atraso e consumo do projeto, a fim de validar os dados das células gerados pela caracterização elétrica. A arquitetura proposta para o circuito de teste é composta por blocos combinacionais que garantem a completa verificação lógica de cada célula da biblioteca. A estrutura básica do circuito de teste é ligeiramente modificada para permitir diferentes modos de operação que permitem avaliação de diferentes dados utilizando simulações elétricas SPICE. Visto que o circuito de teste gera pequeno acréscimo de silício ao projeto final, ele pode ser implementado junto com o ASIC alvo, atuando como um ‘circuito de certificação de biblioteca’. / Cell-based design is the most applied approach in the ASIC market today. This design approach implies re-using pre-customized cell libraries to build more complex digital systems. Therefore the ASIC design efficiency turns to be bounded by the library in use. The use of automatically generated CMOS logic gates in standard cell IC design flow represents an attractive perspective for ASIC design quality improvement. These soft IPs (logic cells generated by software) are the key elements for the novelty libraryfree technology mapping, already proposed in literature and now being adopted by the industry. Library-free technology mapping approach, based on the on-the-fly creation of cells, by software, can provide flexibility to IC designers providing an optimized fit in a particular application. However, such approach represents an IC design flow based on logic cells created on-the-fly by software which have not been previously validated in silicon yet, until the target ASIC is prototyped. In this work, a specific test circuit (testbench) is proposed to validate the full functionality of a set of logic cells, as well as to verify timing and power consumption behaviors, which can be correlated with design timing and power estimations in order to validate the cell data provided by electrical characterization. The proposed architecture for the test circuit is composed by combinational blocks that ensure full logic verification of every library cell. The basic architecture of the test circuit is slightly modified to allow different operating modes which provide distinct data evaluation using SPICE electrical simulations. Since this test circuit brings little silicon overhead to the final design, it can be implemented together with the target ASIC acting as a ‘library certification circuit’.

Projeto baseado em células-padrão é a abordagem mais aplicada no mercado de ASIC atualmente. Essa abordagem de projeto consiste no reuso de bibliotecas de células pré-customizadas para gerar sistemas digitais mais complexos. Portanto a eficiência de um projeto ASIC está relacionado com a biblioteca em uso. A utilização de portas lógicas CMOS geradas automaticamente no fluxo de projeto de circuito integrado baseado em células-padrão representa uma perspectiva atraente para melhorar a qualidade de projeto ASIC. Essas células geradas por software são os elementos-chave dessa nova abordagem de mapeamento tecnológico livre de biblioteca, já proposto na literatura e agora adotado pela indústria. O mapeamento tecnológico livre de biblioteca, baseado na criação de células sob demanda, por software, gera flexibilidade aos projetistas de circuitos integrados, fornecendo ajuste otimizado em aplicações específicas. Contudo, tal abordagem representa um fluxo de projeto de circuito integrado baseado em células lógicas criadas sob demanda por software, as quais não são previamente validadas em silício até que o ASIC alvo seja prototipado. Neste trabalho, um circuito de teste específico é proposto para validar a funcionalidade completa de um conjunto de células lógicas, bem como verificar comportamentos de atraso e consumo, os quais podem ser correlacionados com as estimativas de atraso e consumo do projeto, a fim de validar os dados das células gerados pela caracterização elétrica. A arquitetura proposta para o circuito de teste é composta por blocos combinacionais que garantem a completa verificação lógica de cada célula da biblioteca. A estrutura básica do circuito de teste é ligeiramente modificada para permitir diferentes modos de operação que permitem avaliação de diferentes dados utilizando simulações elétricas SPICE. Visto que o circuito de teste gera pequeno acréscimo de silício ao projeto final, ele pode ser implementado junto com o ASIC alvo, atuando como um ‘circuito de certificação de biblioteca’. / Cell-based design is the most applied approach in the ASIC market today. This design approach implies re-using pre-customized cell libraries to build more complex digital systems. Therefore the ASIC design efficiency turns to be bounded by the library in use. The use of automatically generated CMOS logic gates in standard cell IC design flow represents an attractive perspective for ASIC design quality improvement. These soft IPs (logic cells generated by software) are the key elements for the novelty libraryfree technology mapping, already proposed in literature and now being adopted by the industry. Library-free technology mapping approach, based on the on-the-fly creation of cells, by software, can provide flexibility to IC designers providing an optimized fit in a particular application. However, such approach represents an IC design flow based on logic cells created on-the-fly by software which have not been previously validated in silicon yet, until the target ASIC is prototyped. In this work, a specific test circuit (testbench) is proposed to validate the full functionality of a set of logic cells, as well as to verify timing and power consumption behaviors, which can be correlated with design timing and power estimations in order to validate the cell data provided by electrical characterization. The proposed architecture for the test circuit is composed by combinational blocks that ensure full logic verification of every library cell. The basic architecture of the test circuit is slightly modified to allow different operating modes which provide distinct data evaluation using SPICE electrical simulations. Since this test circuit brings little silicon overhead to the final design, it can be implemented together with the target ASIC acting as a ‘library certification circuit’.

Projeto baseado em células-padrão é a abordagem mais aplicada no mercado de ASIC atualmente. Essa abordagem de projeto consiste no reuso de bibliotecas de células pré-customizadas para gerar sistemas digitais mais complexos. Portanto a eficiência de um projeto ASIC está relacionado com a biblioteca em uso. A utilização de portas lógicas CMOS geradas automaticamente no fluxo de projeto de circuito integrado baseado em células-padrão representa uma perspectiva atraente para melhorar a qualidade de projeto ASIC. Essas células geradas por software são os elementos-chave dessa nova abordagem de mapeamento tecnológico livre de biblioteca, já proposto na literatura e agora adotado pela indústria. O mapeamento tecnológico livre de biblioteca, baseado na criação de células sob demanda, por software, gera flexibilidade aos projetistas de circuitos integrados, fornecendo ajuste otimizado em aplicações específicas. Contudo, tal abordagem representa um fluxo de projeto de circuito integrado baseado em células lógicas criadas sob demanda por software, as quais não são previamente validadas em silício até que o ASIC alvo seja prototipado. Neste trabalho, um circuito de teste específico é proposto para validar a funcionalidade completa de um conjunto de células lógicas, bem como verificar comportamentos de atraso e consumo, os quais podem ser correlacionados com as estimativas de atraso e consumo do projeto, a fim de validar os dados das células gerados pela caracterização elétrica. A arquitetura proposta para o circuito de teste é composta por blocos combinacionais que garantem a completa verificação lógica de cada célula da biblioteca. A estrutura básica do circuito de teste é ligeiramente modificada para permitir diferentes modos de operação que permitem avaliação de diferentes dados utilizando simulações elétricas SPICE. Visto que o circuito de teste gera pequeno acréscimo de silício ao projeto final, ele pode ser implementado junto com o ASIC alvo, atuando como um ‘circuito de certificação de biblioteca’. / Cell-based design is the most applied approach in the ASIC market today. This design approach implies re-using pre-customized cell libraries to build more complex digital systems. Therefore the ASIC design efficiency turns to be bounded by the library in use. The use of automatically generated CMOS logic gates in standard cell IC design flow represents an attractive perspective for ASIC design quality improvement. These soft IPs (logic cells generated by software) are the key elements for the novelty libraryfree technology mapping, already proposed in literature and now being adopted by the industry. Library-free technology mapping approach, based on the on-the-fly creation of cells, by software, can provide flexibility to IC designers providing an optimized fit in a particular application. However, such approach represents an IC design flow based on logic cells created on-the-fly by software which have not been previously validated in silicon yet, until the target ASIC is prototyped. In this work, a specific test circuit (testbench) is proposed to validate the full functionality of a set of logic cells, as well as to verify timing and power consumption behaviors, which can be correlated with design timing and power estimations in order to validate the cell data provided by electrical characterization. The proposed architecture for the test circuit is composed by combinational blocks that ensure full logic verification of every library cell. The basic architecture of the test circuit is slightly modified to allow different operating modes which provide distinct data evaluation using SPICE electrical simulations. Since this test circuit brings little silicon overhead to the final design, it can be implemented together with the target ASIC acting as a ‘library certification circuit’.

Master of Science / Department of Architecture / David Seamon / This thesis uses behavioral mapping to analyze two contrasting spaces in Kansas State University’s Hale Library. One of the spaces is meant for computer use; and the other for general library use, including study-group work. The conceptual approach chosen to describe and analyze these two library spaces is the behavior-setting theory developed by psychologist Roger Barker, who defines behavior settings as independent units of space, with temporal and spatial boundaries, that have “great coercive power over the behaviors that occur within them” (Barker, 1968, p. 17). The behavioral observations for the two Hale Library spaces were analyzed and compared with findings from other studies of library usage and behaviors. In the first chapter of the thesis, I introduce my study topic and discuss recent developments in libraries. In the second chapter, I provide a broad overview of library history and library use. I also overview behavior-setting theory and present examples of research on behavior settings and libraries. In the third chapter, I discuss research methods for this thesis, starting with how library spaces can be described as behavior settings. I then discuss specific methodological procedures involved in the behavioral study of activities in the two library spaces. In the fourth chapter, I discuss the two spaces studied in Hale Library, first, describing their physical features and then discussing their behavior-setting attributes. In the fifth chapter, I present my behavioral observations and compare and contrast the two Hale Library spaces in terms of user behaviors and as behavior settings. In the sixth and final chapter of this thesis, I compare my research results with other library research and offer my speculative ideas on the future of the academic library. The overarching theme of this thesis is evaluating how recent digital technologies have affected libraries, and how traditional library spaces and spaces designated for digital technology can be integrated in future libraries.

This diploma thesis is focused on the automatization of digitization workflow in the National Library of Technology, Prague, Czech Republic. This thesis examines possibilities of digitization processes automatization by means of scripts written in Perl programming language and Apache Ant build tool. The advantages and disadvantages of both solutions are analyzed as well as their suitability for automatization of digitization workflow. Based on the comparison of both solutions, the scripts in Perl programming language are selected as the most suitable solution for automatization of digitization workflow. The question whether Ant build tool could be used for the purpose of automatization of digitization workflow is also answered in this thesis. The Ant build tool could be used for the above-mentioned purpose. However, once the activities in the given process divert from the general scope of tasks provided by the Ant build tool, the complexity of the whole solution increases rapidly. This complexity is given by the necessity to use predefined tasks -- sets of functions which have to be combined to create a functional automatization script. Even though Ant is an extendable tool, it is necessary to understand the Java programming language in order to create a new Ant task successfully. On the other hand, the Perl programming language allows easier customization of the script for the purposes of automatization of digitization workflow. Also, the modularity of the Perl programming language makes it easier to create those scripts and modify, correct or develop them even further.

This study investigated the management of information and communication technologies (ICTs) at academic libraries in selected public universities in Ghana. The purpose for this study was to investigate the managerial processes and challenges in terms of conceptualization, policies, planning, implementation and strategies involved in ICTs adoption in order to formulate strategies for their management in Ghanaian academic libraries. Specifically, the objectives of the study were to review and explore the status and level of ICT diffusion in Ghanaian university; audit the procedures, processes and factors that influence ICT adoption and implementation in Ghanaian university libraries; establish the institutional policies, strategies and human resource that is in place and available for the adoption; determine the factors that hinder the adoption and management of ICTs in Ghanaian university libraries; and design a framework for effective and efficient management of ICTs in Ghanaian public university libraries. The study adopted mixed-method research design approach combining both quantitative and qualitative approaches through the pragmatic worldview to achieve the main purpose of the study. Adopting a survey study design, data was collected from five selected Ghanaian public universities by interviewing the five university librarians/directors, using questionnaires on 313 library staff and making observations within the five libraries. The findings of the study established that the managerial tools/instruments required for effective ICTs management in Ghanaian university libraries include the availability of library ICT policies, a library ICT strategic plan, library ICT installation and maintenance manuals, library ICT integration plans, and standard operations manuals. In addition, adequate funds, skilled manpower, adequate and standard ICT infrastructures among others. However, the study also revealed that there are absence of library ICT policies, lack of processes and procedure guidelines, inadequate funds, lack of management support, inadequate ICT skills among libraries and staff ICT training policies in the academic libraries in Ghana. The study recommends the formulation of ICT policies and strategic plans purposely for the comprehensive management of library ICT systems. Furthermore, the university top management should support their libraries by providing the required resources and motivation for the library managers including the development of stakeholder partnership and collaboration. To galvanise these recommendations, the study proposes a framework for the ICTs adoption and management in Ghanaian university libraries. / Information Science / D. Litt. et Phil. (Information Science)