Low Dropout Regulators (LDOs) are extensively used in portable applications like mobile phones, PDAs and notebooks. These portable applications demand high power efficiency and low output voltage ripple. In addition to these, the radio circuits in these applications demand high power supply rejection (PSR). The output voltage of a conventional DC/DC converter (generally switched mode) has considerable ripple which feeds as input to these LDOs. And the challenge is to suppress these ripples for wide range of frequencies (for radio units) to provide clean supply. Enhanced buffer based compensation is proposed for the fully on-chip CMOS LDO which stabilizes the loop for different load conditions as well as improve the power supply rejection (PSR) until frequencies closer to open loop‟s unity-gain frequency. The stability and PSR are totally valid even for load capacitor varying from 0 to 100 pF. The proposed capacitor-less LDO is fabricated in On-Semi 0.5 μm fully CMOS process. Experimental results confirm a PSR of -30 dB till 420 KHz for the maximum load current of 50mA. The load transients of the chip shows transient glitches less than 90 mV independent of output capacitance.

Sabe-se que à inevitÃvel a ocorrÃncia de acidentes de trÃnsito em rodovias, onde centenas de milhares de veÃculos transitam a cada dia e que, alÃm de gerarem fatalidades, geram danos materiais, fÃsicos e morais Ãs pessoas envolvidas. Quando os acidentes envolvem colisÃes com um poste de distribuiÃÃo de energia elÃtrica, estes sÃo responsÃveis por deixar, em mÃdia, cinco mil residÃncias sem fornecimento de energia de forma imediata. Nestes casos, essa interrupÃÃo no fornecimento pode durar atà quatro horas para os moradores prÃximos ao local da colisÃo devido ao trabalho de substituiÃÃo, bem como gerar altos custos com a reposiÃÃo dos postes. Portanto, faz-se necessÃrio o estudo de um sistema de defensa de postes visando à proteÃÃo destes, bem como salvaguardar os motoristas de veÃculos em caso de colisÃo. O objetivo deste trabalho consiste em avaliar o comportamento do poste e do sistema poste-defensa devido ao choque de veÃculos. Para tanto, sÃo realizadas duas anÃlises paramÃtricas. A primeira consiste na anÃlise modal numÃrica a fim de se determinar a influÃncia de componentes tais como cabos e defensas nos parÃmetros naturais do poste. A segunda consiste na anÃlise transiente paramÃtrica do poste e do conjunto poste-defensa. Neste caso, sÃo variadas a massa do veÃculo, sua velocidade e o tempo de impacto. Estas anÃlises sÃo realizadas no programa comercial, baseado no MÃtodo dos Elementos Finitos, SAP2000 V.14.0. A histÃria no tempo do deslocamento da extremidade livre do poste à comparada entre os diversos modelos, bem como com os resultados das amplitudes das cargas dinÃmicas aplicadas de forma estÃtica. Dos resultados observa-se que a defensa cumpre seu papel diminuindo a possibilidade de colapso devido aumentar as frequÃncias naturais e afastando-as das frequÃncias de excitaÃÃo das cargas de impacto. Da anÃlise transiente conclui-se que a defensa aumenta a rigidez do sistema reduzindo os deslocamentos. / It is known that is inevitable the incidence of traffic accidents in highways, where hundreds of thousands of vehicles pass daily. These accidents can cause material damages, physical and moral injuries to involved persons, besides fatalities. When collisions are into an electric distribution pole, these are responsible by five thousand residences without electric power immediately. In this case, the stop in supplying can take four hours to residents who live close to accident site due to replacement work, as well as to generating high costs to replace the poles. So, it is necessary to study a system that protects the pole, as well as safeguards the vehicles drivers in case of collision. The objective of this work is to evaluate the behavior of pole and of system pole-defence due to the vehicles shock. Two parametric analyses are carried out. The first one is the numerical modal analysis in order to determine the influence of components like cables and defence in the pole natural parameters. The second one is the transient parametric analysis of pole and of pole-defence system. In this case, the vehicle mass and his impact time are varied. These analyses are executed in the commercial program based on the Finite Elements Method, SAP2000 V.14.0. The displacement history of pole free end is compared between the several models, as well as with the results obtained when the dynamic load maximum value is applied statically. From results it is noticed that defence carries out his paper reducing the possibility of collapse due to increasing the natural frequencies and making away from excitation frequencies of impact loads. From transient analysis it is concluded that defence raises the rigidity of the system by reducing the displacements.

The miniaturization of dc–dc switch-mode power supplies (SMPS) is of a key importance in volume-sensitive portable devices, such as cell phones, tablet computers, and digital cameras. In these systems, multiple SMPS are required to provide well regulated voltage and power to various electronic components such as the central processing unit (CPU) and random-access memory (RAM). The combined volume, weight, and surface area footprint of these SMPS is usually the largest component. Traditionally, SMPS volume reduction has been achieved through increased switching frequencies; however, for power-sensitive applications this is undesirable due to the increased switching losses. This thesis presents two alternative, power-efficient, SMPS miniaturization methods: one control and one topology based. The presented controller recovers from load transients with virtually minimum possible output voltage deviation, reducing the reactive component size. The controller utilizes a simple algorithm, requiring no knowledge of the converter parameters and virtually no processing power. The simplicity of the control concept enabled the design of an area and power efficient integrated circuit (IC) implementation. The entire IC is implemented in a CMOS 0.18µm process on a 0.26 mm2 silicon area, which is comparable to the state-of-the-art analog solutions. For the experimental system the deviation (output capacitor size) is about four times smaller than that of a fast PID compensator having a 1/10th of the switching frequency bandwidth. The second solution is a complementary converter topology that has a smaller output filter volume, improved dynamic response, and lower switching losses compared to the state-of-the-art solutions. To reduce the volume and switching losses, the input-to-output voltage difference is decreased with a capacitive attenuator that replaces the input filter capacitor and has approximately the same volume. Both the attenuator and the downstream buck converter share the same set of switches, minimizing conduction losses. A single multi-mode digital controller governs operation of both stages, seamlessly regulating the output and input center-tap voltages. Experiments with a 5–1.5-V, 2.5-A, 1-MHz prototype show that, compared to the conventional buck, the merged topology has 43% smaller inductor, 36% smaller output capacitor, up to 30% lower power losses, and a 25% faster transient response.

The miniaturization of dc–dc switch-mode power supplies (SMPS) is of a key importance in volume-sensitive portable devices, such as cell phones, tablet computers, and digital cameras. In these systems, multiple SMPS are required to provide well regulated voltage and power to various electronic components such as the central processing unit (CPU) and random-access memory (RAM). The combined volume, weight, and surface area footprint of these SMPS is usually the largest component. Traditionally, SMPS volume reduction has been achieved through increased switching frequencies; however, for power-sensitive applications this is undesirable due to the increased switching losses. This thesis presents two alternative, power-efficient, SMPS miniaturization methods: one control and one topology based. The presented controller recovers from load transients with virtually minimum possible output voltage deviation, reducing the reactive component size. The controller utilizes a simple algorithm, requiring no knowledge of the converter parameters and virtually no processing power. The simplicity of the control concept enabled the design of an area and power efficient integrated circuit (IC) implementation. The entire IC is implemented in a CMOS 0.18µm process on a 0.26 mm2 silicon area, which is comparable to the state-of-the-art analog solutions. For the experimental system the deviation (output capacitor size) is about four times smaller than that of a fast PID compensator having a 1/10th of the switching frequency bandwidth. The second solution is a complementary converter topology that has a smaller output filter volume, improved dynamic response, and lower switching losses compared to the state-of-the-art solutions. To reduce the volume and switching losses, the input-to-output voltage difference is decreased with a capacitive attenuator that replaces the input filter capacitor and has approximately the same volume. Both the attenuator and the downstream buck converter share the same set of switches, minimizing conduction losses. A single multi-mode digital controller governs operation of both stages, seamlessly regulating the output and input center-tap voltages. Experiments with a 5–1.5-V, 2.5-A, 1-MHz prototype show that, compared to the conventional buck, the merged topology has 43% smaller inductor, 36% smaller output capacitor, up to 30% lower power losses, and a 25% faster transient response.