TO achieve high level of integration in order to reduce cost, heterodyne architecture has made way for low-IF and zero-IF (direct conversion) receiver architectures. However, a very serious issue in implementing both zero and low-IF receiver is of local oscillator (LO) pulling. Another challenge is on-chip generation of high-precision quadrature LO signals for image-rejection. We have addressed both these issues in this thesis. Regarding the first problem, we have developed a lowpower frequency multiplication technique which uses a low frequency ring oscillator and multiplies its frequency in power e cient way to generate the desired frequency. We then use this differential LO signal to generate high-precision quadrature phases by using polyphase filter and an injection-locked quadrature oscillator. Design examples are presented for 2.4 GHz band of IEEE 802.15.4 standard which is a low-data rate WPAN standard. The standard o ers relaxed performance specifications in order to help achieve low power of operation. Contributions in the thesis • The problem of local oscillator (LO) pulling can be addressed by running LO at a much reduced frequency and use a frequency multiplier (FM) to generate the desired frequency. Also, use of low-frequency LO saves power in VCO and helps eliminate first few dividers leading to significant power savings. In addition, the entire frequency synthesizer can be run at a lower supply voltage saving additional power. The frequency multiplier involves combining edges from the lower frequency ring oscillator. It improves upon the prior work by proposing a new lower-power edge-combiner. The overall power is reduced by exploiting the relaxed phase noise specification of IEEE 802.15.4 standard. Simulations using SpectreRF show that the circuit consumes only 550 ｵW of power in 0.13 ｵm RF-CMOS technology with 1.2 V supply voltage, and provides 950 VP-P sinusoidal output with phase noise of -85.5 dBc/Hz at 1 MHz offset. • An injection-locking based quadrature desensitization circuit is designed for precision quadrature generation. The differential (two phase) output of the frequency multiplier is fed to a polyphase filter to generate nearly quadrature signals. Output of polyphase filter is in turn fed to the desensitizer circuit to obtain high-precision quadrature signals. Designed for 2.4 GHz band in 0.13 µm RF-CMOS technology, it achieves a phase error of 0.5 for 1% mismatch in LC tanks. It achieves a phase noise of -84.3 dBc/Hz at 1 MHz o set and provides quadrature sinusoids of 475 mV amplitude while consuming 1.56 mW of power. • We have analyzed the popular cross-coupled LC-VCOs to generate quadrature sinusoids. In practical LC-oscillators built using low/moderate quality factor on-chip inductors, the actual frequency of oscillation is a little less than 1/2pvLC . This is known as Groszkowski effect. On the other hand, in quadrature oscillator topologies, consisting of two, cross-coupled, negative resistance LC-VCOs using parallel coupling transistors, an upward shift in frequency of oscillation from the free-running frequency of each LC-VCO is observed. This is because in order to satisfy the Barkhausen’s criteria, the LC-tanks have to operate at a frequency away from the frequency of resonance. This e ect called as quadrature detuning effect results in higher phase noise and reduced amplitude. We have shown that the old treatment given in literature is quite inaccurate for practical LC oscillators that are built using low/mo derate Q on-chip inductors. Also the prior work ignores Groszkowski effect which could be significant for low Q LC tanks. We have provided simple, accurate and closed-form expressions of associated frequency-shifts and amplitude of oscillation including both the effects. Our results show excellent match with results obtained from SpectreRF and Matlab simulations.

The competitive market of wireless communication devices demands low power and low cost RF solutions. A quadrature local oscillator (LO) is an essential building block for most transceivers. As the CMOS technology scales deeper into the nanometer regime, design of a low-power low-voltage quadrature LO still poses a challenge for RF designers. This dissertation investigates a new quadrature LO topology featuring a transformer-based voltage controlled oscillator (VCO) stacked with a divide-by-two for low-power low-voltage wireless applications. The transformer-based VCO core adopts the Armstrong VCO configuration to mitigate the small voltage headroom and the noise coupling. The LO operating conditions, including the start-up condition, the oscillation frequency, the voltage swing and the current consumption are derived based upon a linearized small-signal model. Both linear time-invariant (LTI) and linear time-variant (LTV) models are utilized to analyze the phase noise of the proposed LO. The results indicate that the quality factor of the primary coil and the mutual inductance between the primary and the secondary coils play an important role in the trade-off between power and noise. The guidelines for determining the parameters of a transformer are developed. The proposed LO was fabricated in 65 nm CMOS technology and its die size is about 0.28 mm2. The measurement results show that the LO can work at 1 V supply voltage, and its operation is robust to process and temperature variations. In high linearity mode, the LO consumes about 2.6 mW of power typically, and the measured phase noise is -140.3 dBc/Hz at 10 MHz offset frequency. The LO frequency is tunable from 1.35 GHz to 1.75 GHz through a combination of a varactor and an 8-bit switched capacitor bank. The proposed LO compares favorably to the existing reported LOs in terms of the figure of merit (FoM). More importantly, high start-up gain, low power consumption and low voltage operation are achieved simultaneously in the proposed topology. However, it also leads to higher design complexity. The contributions of this work can be summarized as 1) proposal of a new quadrature LO topology that is suitable for low-power low-voltage wireless applications, 2) an in-depth circuit analysis as well as design method development, 3) implementation of a fully integrated LO in 65 nm CMOS technology for GPS applications, 4) demonstration of high performance for the design through measurement results. The possible future improvements include the transformer optimization and the method of circuit analysis. / Ph. D.