The first topic of this thesis is a practical load-optimized VCO design for low-jitter 5V 500 MHz digital phase-locked loop. Besides the low jitter advantage, the design also possesses another feature, i.e., fast locked time. The second topic is the half-swing PLA circuit. An additional 1/2 VDD voltage source and buffering transmission gates are inserted between the NOR planes of PLAs to erase the racing problem and shorten the rise delay as well as the fall delay of the output response such that the speed is enhanced and the dynamic power is reduced. The third topic is a novel design of a the 1.0 GHz pipelining 8-bit CLA based on the architecture we mentioned in the second topic. The operating clock frequency is 1.0 GHz and the output of the addition of two 8-bit binary numbers is done in 2 cycles ( 2.0 ns ).

No description available.

As an increasing number of distributed power generation systems (DPGS) are being connected to the utility grid, there is a growing requirement for the DPGS to be able to ride through short grid disturbances. This requires improvements to be made to the grid-side control scheme of the DPGS. An important part of the grid-side control scheme is the grid synchronization method, which is responsible for tracking the phase angle of the grid voltage vector. The state-of-the-art grid synchronization methods being used today are phase-locked loops. This thesis presents a modified phase-locked loop which is more robust towards grid disturbances. It consists of a multi-block adaptive notch filter (ANF) integrated into a conventional three-phase synchronous reference frame phase-locked loop (SRF-PLL). The addition of the multi-block ANF to the system allows it to become frequency adaptive. Also, since the multi-block ANF consists of multiple ANF blocks in parallel with one another, the system is able to remove multiple input signal distortions. Thus, the proposed system is able to eliminate the double frequency ripple that is caused in the conventional three-phase SRF-PLL by input unbalance, as well as harmonic errors, despite the presence of frequency variations in the input signal. Simulation results found using Matlab/Simulink, and experimental results found using the dSPACE DS1103 DSP board, demonstrate the feasibility of the modified SRF-PLL. Also, the modified SRF-PLL is compared to a conventional three-phase SRF-PLL, as well as to a conventional three-phase SRF-PLL with a simple notch filter, and the advantages of the modified SRF-PLL are discussed. / Thesis (Master, Electrical & Computer Engineering) -- Queen's University, 2008-12-17 12:38:02.589

No description available.

Thesis (Honors)--College of William and Mary, 2008. / Includes bibliographical references (leaf 28). Also available via the World Wide Web.

Thesis (M.S.)--Oregon State University, 2009. / Printout. Includes bibliographical references (leaves 43-45). Also available on the World Wide Web.

Thesis (M.S.)--Oregon State University, 2006. / Printout. Includes bibliographical references (leaves 29-30). Also available on the World Wide Web.

Thesis (M.S.)--Montana State University--Bozeman, 2005. / Typescript. Chairperson, Graduate Committee: Steven R. Shaw. Includes bibliographical references (leaf 42).

Bamberg, Univ., Diss., 2004.

Thesis (MScIng)--University of Stellenbosch, 2008. / Bibliography. Also available via the Internet.