No description available.

An analytical threshold criterion in approximation has been developed for the basic phase-locked loop demodulator utilizing quasi-linearization technique. The analysis is based on assumptions that the loop is excited by an input FM signal and additive white Gaussian noise. This paper defines the threshold criterion by the characteristics of maximum demodulating sensitivity limit. Finally, the effects of the modulation indeces and loop parameters on the threshold characteristics are discussed from a theoretical and practical point of view. / Master of Science

No description available.

In this thesis, novel regimes of mode locking in quantum dot semiconductor laser diodes have been investigated by exploiting the unique features offered by quantum dots. Using an unconventional approach, the role of excited state transitions in the quantum dots was exploited as an additional degree of freedom for the mode locking of experimental quantum dot lasers. For the first time, passive mode locking via ground (1260nm) or excited state (1190nm) was demonstrated in a quantum dot laser. Picosecond pulses were generated at a repetition rate of 21GHz and 20.5GHz, for the ground and excited states respectively, with average powers in excess of 25mW. Switching between these two states in the mode-locking regime was achieved by changing the electrical biasing conditions, thus providing full control of the operating spectral band. A novel regime for mode locking in a quantum-dot laser was also investigated, where the simultaneous presence of cw emission in the excited-state band at high injection current levels, dramatically reduced the duration of the pulses generated via the ground state, whilst simultaneously boosting its peak power. This represents a radically different trend from the one typically observed in mode-locked lasers. From this investigation, it was concluded that the role of the excited state can not be neglected in the generation of ultrashort pulses from quantum-dot lasers. Stable passive mode locking of a quantum-dot laser over an extended temperature range (from 20ºC to 80ºC) was also demonstrated at relatively high output average powers. It was observed that the pulse duration and the spectral width decreased significantly as the temperature was increased up to 70ºC. The process of carrier escape in the absorber was identified as the main contributing factor that led to a decrease in the absorber recovery time as a function of increasing temperature which facilitated a decrease in the pulse durations. These results are shown to open the way for the ultimate deployment of ultra stable and uncooled mode-locked semiconductor diode lasers.

Complex digital circuits such as microprocessors typically require support circuitry that has traditionally been realized using analog or mixed-signal macros. PLL circuits are used in many integrated applications such as frequency synthesizers and inter-chip communication interfaces. As process technologies advance and grow in complexity, the challenge of maintaining required analog elements and performance for use in circuits such as PLLs grows. Recently, digital PLL (DPLL) has emerged as an alternative to analog PLL to overcome many constraints such as low supply voltage, poor analog transistor behavior, larger area due to integrated capacitor and process variability. However, DPLLs have high deterministic jitter due to quantization noise of time-to-digital converter (TDC) and digitally-controlled oscillator (DCO) and struggle with random jitter of oscillator. In this thesis, hybrid analog/digital proportional/integral control is used to suppress TDC quantization error and digital phase accumulation techniques to mitigate DCO quantization error. VCO phase noise was reduced using an embedded voltage-mode feedback. This feedback loop is implemented by using a switched-C circuit which converts frequency to current. Designed in a 130nm CMOS process, the proposed DPLL generates more than 1GHz output frequency with low input frequency and achieves superior jitter performance compared to conventional DPLL in simulations. / Graduation date: 2013

The use of resonant CMOS frequency dividers with direct injection in frequencysynthesizers has increased in recent years due to their lower power consumptioncompared to conventional digital prescalers. The theoretical and experimentalaspects of these dividers have received great attention. This masters thesis workis a continuation of earlier work, based on the fundamentals of Injection-LockedFrequency Dividers (ILFD’s). The LC CMOS ILFD with direct injection is wellknownfor its divide-by-2 capability. However, it does not divide well by oddnumbers. The goal of this master thesis work is to modify the LC CMOS ILFDwith direct injection so that it can divide equally well by odd and even integers.In this master thesis report, an introduction to the basic concepts behindInjection-Locked frequency dividers is first presented. Some of the previous workand the background of a reference LC CMOS ILFD design are studied. The author,studied the reference design, and the experimental setup used for characterizingit’s locking behavior. The algorithm used to characterize the locking behavior ofthis ILFD are explored to reproduce the results for divide-by-even numbers for theexisting ILFD topology. Using a Spice model these results are also reproduced insimulations.Over the years, numerous ILFD circuit topologies have been proposed, most ofwhich have been optimized for division by even numbers, especially divide-by-2.It has been more difficult to realize division by odd numbers, such as divide-by-3.This master thesis work develops a simple modification to an LC CMOS injectionlocked frequency divider (ILFD) with direct injection, which gives it a wide lockingrange both in the “divide-by-odd number” mode and in the conventional “divideby-even number” regime, thereby opening up applications which require frequencydivision by an odd number. The work presents the circuit architecture, SPICEsimulations and experimental validation.

A successive approximation register (SAR) circuit is adopted to control the digital delay line in the delay-locked loop (DLL) to achieve very fast locking effect in this proposed thesis. And in order to get low power consumption results, a loop state controller (LSC) is utilized to disable most of circuit. Because it is more easily to design and the advantages of high stability of delay-locked loop (DLL) compared to phase-locked loop (PLL), delay-locked loop (DLL) is more widely used in the adjustment of the clock error in the high frequency situation. This proposed delay locked loop (DLL) is added a register and a multiplexer in the feedback path. And the multiplexer does select which n-bit digital control code shall be read into the delay line; as the loop is locked, the path goes through the register is chosen to enter the sleep state ,and disable part of the circuit to make it into power saving mode. When entering the sleep state, the register provides the fixed input code; the phase error comparator (PEC) will keep tracking whether the frequency changes due to process, voltage, temperature and load (PVTL) variation uninterruptedly. Once there is something changed, the PEC will send a signal to inform the loop state controller (LSC) to enable the circuit from the sleep state, when the clock has to be locked again. And it just has 6 cycles time to relock, the lock range is form 150MHz to 900MHz. The power consuming are 15mW in lock mode and 9mW in sleep mode.

Το αντικείμενο της παρούσας διπλωματικής εργασίας είναι ο σχεδιασμός και η υλοποίηση ενός ταλαντωτή εμβολής, ο οποίος θα μπορεί να χρησιμοποιηθεί και ως διαιρέτης συχνοτήτων. Ο ταλαντωτής και ο διαιρέτης συχνοτήτων, αποτελούν εξέχουσας σημασίας δομικά στοιχεία των RF πομποδεκτών και τοποθετούνται κατά κύριο λόγο μέσα στο βρόχο κλειδώματος φάσης-PLL, ο οποίος επιλέγεται ως συνθέτης συχνοτήτων στα περισσότερα ασύρματα τηλεπικοινωνιακά συστήματα. Αφού μελετήσαμε τη δομή και τις κυριότερες τοπολογίες που χρησιμοποιούνται στη σχεδίαση των ταλαντωτών, προχωρήσαμε στην ανάλυση της εφαρμογή της μεθόδου της εμβολής (injection locking), με σκοπό τη βελτίωση των χαρακτηριστικών της εξόδου τους και ιδιαίτερα τη μείωση του θορύβου φάσης. Επίσης, περιγράφονται τα βασικά χαρακτηριστικά των αναλογικών και των ψηφιακών διαιρετών, ενώ δίνεται ιδιαίτερη έμφαση στην ανάλυση της λειτουργίας των αναλογικών διαιρετών συχνότητας που βασίζονται σε ταλαντωτές εμβολής και είναι ευρύτερα γνωστοί ως injection-locked διαιρέτες συχνότητας (ILFDs). Η επιλογή για περαιτέρω μελέτη και υλοποίηση ενός Colpitts και ενός διαφορικού ταλαντωτή, βασίστηκε στα πλεονεκτήματα που παρουσιάζουν οι συγκεκριμένες τοπολογίες, με αποτέλεσμα την ευρεία χρήση τους σε RF εφαρμογές υψηλών συχνοτήτων. Επίσης οι ταλαντωτές εμβολής που προκύπτουν από τους ταλαντωτές αυτούς, επιδεικνύουν χαμηλή κατανάλωση ισχύος και πολύ καλή συμπεριφοράς ως προς τον θόρυβο φάσης. Ως συχνότητα λειτουργίας των προτεινόμενων κυκλωμάτων, επιλέχθηκε η πολύ σημαντική για τα ασύρματα συστήματα τηλεπικοινωνιών, συχνότητα των 5GHz. Προτείνεται και υλοποιείται λοιπόν ένας Colpitts ταλαντωτής και ο αντίστοιχος ταλαντωτής εμβολής, όπου όπως αποδεικνύεται τόσο από τις εξομοιώσεις όσο και από τα πειραματικά αποτελέσματα, μπορεί να λειτουργεί ως διαιρέτης συχνότητας δια-2 (Divide-by-2 ILFD). Από τα αποτελέσματα που προέκυψαν από τη μέτρηση του υλοποιημένου ταλαντωτή εμβολής, γίνεται ακόμη αντιληπτό ότι ο θόρυβος φάσης είναι εμφανώς βελτιωμένος, όπως αναμενόταν λόγω της εφαρμογής του σήματος εμβολής. Τέλος, σχεδιάστηκε και εξομοιώθηκε ένας διαφορικός ταλαντωτής (differential oscillator), από τον οποίο με κατάλληλη τροποποίηση της τοπολογίας του, προέκυψε ένας injection-locked divide-by-2 διαιρέτης συχνότητας. Το συγκεκριμένο κύκλωμα χρησιμοποιείται ευρέως για τη λειτουργία της διαίρεσης δια-2, εξαιτίας του ότι η τοπολογία του παρέχει ένα φυσικό divide-by-2 injection σημείο. / The subject of the present diplomatic project is the design and implementation of an injection locked oscillator, which might also be used as a frequency divider. The oscillator and the frequency divider, constitute distinguished important structural elements of RF transceivers and are mostly placed into the phase-locked-loop (PLL), which is selected as frequency synthesizer in most wireless telecommunications systems. After we studied the structure and the main topologies used in the design of oscillators, we advanced in the analysis and the application of injection locking method, aiming at the improvement of characteristics of their output and particularly the reduction of phase noise. Also, the basic characteristics of analog and digital dividers are described, while particular emphasis is given in the analysis of operation of analog frequency dividers that is based on injection-locked oscillators, more widely known as injection-locked frequency dividers (ILFDs). The choice for further study and implementation of a Colpitts and differential oscillator, was based on the advantages of the particular topologies, which result in their wide use in high-frequencies RF applications. Also the injection-locked oscillators that result from these oscillators, demonstrate low power consumption and very good behavior as far the phase noise. As operation frequency for the proposed circuits, was selected the very important for the wireless telecommunications systems, frequency of 5GHz. Therefore, it is proposed and implemented a Colpitts oscillator and the corresponding injection-locked oscillator, where as it is proved by the simulations as much as by the experimental results, can function as a divide-by-2 injection-locked frequency divider. From the results that resulted from the measurement of implemented injection-locked oscillator, it becomes clear that the phase noise is obviously improved, as it was expected due to the application of the injection signal. Finally, a differential oscillator was designed and simulated, from which with suitable modification of its topology, resulted a divide-by-2 injection-locked frequency divider. This particular circuit is used widely for the operation of division by-2, because its topology provides a natural divide-by-2 injection point.

A true linearized interferometric intensity modulator for pulsed light has been proposed and experimentally presented in this thesis. This has been achieved by introducing a mode-locked laser into one of the arms of a Mach-Zehnder interferometer and injection-locking it to the input light (which is pulsed and periodic). By modulating the injection-locked laser, and combining its output light with the light from the other arm of interferometer in quadrature, one can achieve true linearized intensity modulator. This linearity comes from the arcsine phase response of the injection-locked mode-locked laser (as suggested by steady-state solution of Adler's equation) when it is being modulated. Mode-locked lasers are fabricated using a novel AlGaInAs-InP material system. By using the BCB for planarization and minimizing the metal pad size and directly modulating the laser, we have achieved very effective fundamental hybrid mode-locking at the repetition rate of ~ 23 GHz. This laser also provided the short pulses of 860 fs and 280 fs timing jitter integrated from 1 Hz- 100 MHz. The linearized intensity modulator has been built by using two identical two-section mode-locked lasers with the same length, one as the slave laser in one of the arms of the Mach-Zehnder interferometer injection-locked to the other one as the master which is the input light to the modulator. A low V? of 8.5 mV is achieved from this modulator. Also the current of the gain section or the voltage of the saturable absorber section of the slave laser has been used to apply the modulation signal. A spur free dynamic range of 70 dB.Hz2/3 is achieved when modulating the modulator through the saturable absorber. Modulating the saturable absorber provides a reduced third-order intermodulation tone with respect to modulating the gain. This is simply because of the unwanted amplitude modulation created when modulating the gain section current. Finally an improved design is proposed and demonstrated to improve the modulator performance. This is achieved by introducing a third section to the laser. Using the impurity free vacancy disordering technique the photoluminescence peak of this section is blue-shifted selectively and therefore there would not be any absorption in that passive section. By applying the modulation signal to this passive section rather than applying it to the gain section or saturable absorber section, the amplitude and phase modulation could be decoupled. The experimental results have presented here and an almost six-fold reduction in V? and 5 dB improvement in spur free dynamic range have been achieved. The proposed and demonstrated configuration as an analog optical link has the potential to increase the performance and resolution of photonic analog-to-digital converters.

International Telemetering Conference Proceedings / October 18-21, 2004 / Town & Country Resort, San Diego, California / FLL’s are extensively used for fast carrier synchronization. A common approach to meet the wide acquisition range and sufficiently small tracking error requirements is to adopt the wide or narrow band FLL loop in the acquisition and tracking modes and direct switching the loop. The paper analyze the influence of direct switching on performance, including the narrow band loop convergence, transition time etc. and propose applying the Kalman filtering theory to realize the seamless switching (SS) with time-varying loop gains between the two different loop tracking state. The SS control gains for the high dynamic digital spread spectrum receiver is derived. Simulation results for the SS compared to the direct switching demonstrate the improved performance.