published_or_final_version / Electrical and Electronic Engineering / Master / Master of Philosophy

Στη διατριβή αυτή προτείνονται, αναλύονται και υλοποιούνται εναλλακτικές τοπολογίες για δυο από τα κύρια υποσυστήματα ενός πομποδέκτη, τον τοπικό ταλαντωτή και τον ενισχυτή χαμηλού θορύβου. Το κύριο σύστημα που εξετάζεται είναι αυτό του τοπικού ταλαντωτή, όπου μελετούνται και υλοποιούνται τοπολογίες ταλαντωτών και βρόχων που λειτουργούν υπό εμβολή, με κύριο προσανατολισμό την ελαχιστοποίηση του θορύβου φάσης. Ο προτεινόμενος βρόχος εμβολής προσφέρει την δυνατότητα χρησιμοποίησής του σε multiband συστήματα με ταυτόχρονη μάλιστα λειτουργία στις ζώνες των 2.4 GHz και 5.2 GHz για την περίπτωση των ασύρματων τοπικών δικτύων. Ένας τέτοιος βρόχος μπορεί να συμβάλει καθοριστικά στην ελαχιστοποίηση του μεγέθους και της κατανάλωσης του συνολικού multiband συστήματος. Προτείνεται και υλοποιείται ένας ταλαντωτής εμβολής (injection-locked oscillator) και διερευνάται η δυνατότητά του να λειτουργεί παράλληλα και ως μίκτης δίνοντας ένα κύκλωμα πολλαπλών λειτουργιών και εφαρμογών. Το κύκλωμα αυτό ανάλογα με τα σήματα που εμφανίζονται στην είσοδό του λειτουργεί ως απλός ταλαντωτής, ως ταλαντωτής εμβολής, ή ως ίδιο-ταλαντούμενος μίκτης. Προτείνεται και υλοποιείται βρόχος εμβολής (injection-locked phase-locked loop, ILPLL) και μελετάται η βελτίωση στον θόρυβο φάσης και την περιοχή κλειδώματος. Στα πλαίσια των ILPLL μελετώνται και υλοποιούνται βρόχοι εμβολής στην θεμελιώδη συχνότητα και βρόχοι υπό-αρμονικής (sub-harmonic) εμβολής (s-ILPLL). Ο βρόχος υπό-αρμονικής εμβολής χρησιμοποιεί σήμα εμβολής στα 2.5 GHz και παράγει συχνότητα εξόδου 5 GHz. Στα πλαίσια της διερεύνησης του θορύβου φάσης σε συστήματα τοπικών ταλαντωτών μελετάται η διάταξη του συνθέτη διπλού βρόχου και αναπτύσσεται μία πρωτότυπη τοπολογία με καλύτερα χαρακτηριστικά στον θόρυβο φάσης σε σύγκριση με τις κλασικές αρχιτεκτονικές διπλού βρόχου. Σε όλες τις παραπάνω διατάξεις, παρουσιάζονται, η μαθηματική ανάλυση για τον θόρυβο φάσης και τα αποτελέσματα των θεωρητικών υπολογισμών. Η ορθότητα των προτάσεων και η λειτουργία των προτεινόμενων διατάξεων επαληθεύεται με μετρήσεις των πειραματικών πρωτοτύπων. Τέλος, στα πλαίσια της διατριβής προτείνεται ένας ενισχυτής χαμηλού θορύβου που περιλαμβάνει κύκλωμα ελέγχου του κέρδους, το οποίο δίνει την δυνατότητα στο σύστημα να «επιλέξει» την επιθυμητή ενίσχυση ανάλογα με τις συνθήκες, μειώνοντας έτσι σημαντικά την κατανάλωση σε περιπτώσεις όπου αυτό είναι δυνατό. Περιλαμβάνει επίσης και φίλτρο απόρριψης ειδώλου που ελέγχεται από εξωτερική τάση συντονισμού. / In this dissertation we propose, study and develop alternative topologies for two of the most important blocks of a Front-End, the Local Oscillator and the Low Noise Amplifier. We are mainly concerned with the analysis of various local oscillator topologies, studying the phase noise and the injection-locking performance of oscillators and phase-locked loops. The overall performance of the experimental design demonstrates the applicability of the proposed approach to the development of dual-band synthesizers (2.4 GHz and 5.2 GHz), which constitute very important subsystems for modern multiband/multistandard transceivers in WLAN applications. We propose and develop an injection locked oscillator (ILO) and investigate the ability to operate simultaneously as a mixer resulting in a multifunctional circuit. The proposed circuit topology operates as: a) a free-running oscillator, b) both an injection-locked oscillator and a subharmonic injection-locked oscillator (s-ILO), c) both a self-oscillating mixer and a harmonic self-oscillating mixer (h-SOM), and d) a subharmonic injection-locked self-oscillating mixer (s-ILSOM). We propose and develop a different approach for ILPLL design at 5 GHz by applying a technique used in optical communications. We newly address the phase-noise analysis using the loop linear model and compare the results with previously reported work. Furthermore, we address the phase noise improvement of subharmonic ILPLLs, especially for the 5-GHz band. Theoretical analysis and computer calculations demonstrate an improved performance for phase noise and power consumption. We present the analysis and experimental evaluation of a modified dual-loop phase locked loop synthesizer, using the phase noise transfer functions resulting from the linear model of the synthesizer. The different arrangement in the high frequency loop, in contrast to previous reported series-connected dual-loop topologies, offers various advantages, such as improved phase noise, finer resolution and lower spurious levels. Discrete elements are used to implement a prototype system for testing. This adds to the flexibility of the design and allows for experimental optimisation of the loop trade-offs. The synthesizer generates signals in the 4850 MHz to 5050 MHz range with a 10 MHz resolution and can match the specifications for wireless LANs operating at 5 GHz. The design resulted in a prototype with very good characteristics suitable for future integration. For all the proposed topologies we present the mathematical analysis and calculated results for the phase noise. Measurement results illustrate the validity of the proposed analyses, demonstrate the main characteristics, and confirm the feasibility of the proposed systems. Finally, a bipolar Low Noise Amplifier (LNA) is designed in this thesis. The IC contains the LNA core, an externally programmed bias network and an image rejection filter. The externally programmed bias network allows the user to select the bias current in an adaptive manner, depending upon the requirements of the individual system. (Low NF, high gain, low consumption etc). Furthermore, the chip can be powered down by sending an appropriate bit stream to the bias network.

The rapid growth of the market for short-range wireless devices, with standards such as Bluetooth and Wireless LAN (IEEE 802.11) being the most important, has created a need for highly integrated transceivers that target drastic power and area reduction while providing a high level of integration. The radio section of the devices designed to establish communications using these standards is the limiting factor for the power reduction efforts. A key building block in a transceiver is the frequency synthesizer, since it operates at the highest frequency of the system and consumes a very large portion of the total power in the radio. This dissertation presents the basic theory and a design methodology of frequency synthesizers targeted for short-range wireless applications. Three different examples of synthesizers are presented. First a frequency synthesizer integrated in a Bluetooth receiver fabricated in 0.35μm CMOS technology. The receiver uses a low-IF architecture to downconvert the incoming Bluetooth signal to 2MHz. The second synthesizer is integrated within a dual-mode receiver capable of processing signals of the Bluetooth and Wireless LAN (IEEE 802.11b) standards. It is implemented in BiCMOS technology and operates the voltage controlled oscillator at twice the required frequency to generate quadrature signals through a divide-by-two circuit. A phase switching prescaler is featured in the synthesizer. A large capacitance is integrated on-chip using a capacitance multiplier circuit that provides a drastic area reduction while adding a negligible phase noise contribution. The third synthesizer is an extension of the second example. The operation range of the VCO is extended to cover a frequency band from 4.8GHz to 5.85GHz. By doing this, the synthesizer is capable of generating LO signals for Bluetooth and IEEE 802.11a, b and g standards. The quadrature output of the 5 - 6 GHz signal is generated through a first order RC - CR network with an automatic calibration loop. The loop uses a high frequency phase detector to measure the deviation from the 90° separation between the I and Q branches and implements an algorithm to minimize the phase errors between the I and Q branches and their differential counterparts.

The high-speed clock and data recovery (CDR) circuit is a key building block of modern communication systems with applications spanning a wide range from wireline long-haul networks to chip-to-chip and backplane communications. In this dissertation, our focus is on the modelling, design and analysis of devices and circuits used in this versatile system in CMOS technology. Of these blocks, we have identified the voltage-controlled oscillator (VCO) as an important circuit that contributes to the total noise performance of the CDR. Among different solutions known for this circuit, LC-VCO is acknowledged to have the best phase noise performance, due to the filtering characteristic of the LC tank circuit. We provide details on modelling and characterization of a special type of varactor, the accumulation-mode MOS varactor, used in the tank circuit as a tuning component of these types of VCOs. We propose a new sub-circuit model for this type of varactor, which can be easily migrated to other technologies as long as an accurate model exists for MOS transistors. The model is suitable whenever the numerical models have convergence problems and/or are not defined for the specific designs (e.g., minimum length structures). The model is verified directly using measurement in a standard CMOS 0.13µm process, and indirectly by comparing the tuning curves of an LC-VCO designed in CMOS 0.13µm and 0.18µm processes. Using a varactor, a circuit technique is proposed for designing a narrowband tuneable clock buffer, which can be used in a variety of applications including the CDR system. The buffer automatically adjusts its driving bandwidth to that of the VCO, using the same control voltage that controls the frequency of the VCO. In addition, a detailed analysis of the impact of large output signals on the tuning characteristics of the LC-VCO is performed. It is shown that the oscillation frequency of the VCO deviates from that of an LC tank.

Chemical modifications of oligonucleotides provide an important tool to understand how the natural substrate works as well as how to improve their biochemical and biological properties as potential therapeutics and diagnostics. Our carba-LNA (2',4'-carba-bridged Locked Nucleic Acid) modified oligo-DNA or -RNA have been found to be useful to modulate oligo-RNA and -DNA activity. This thesis is based on four papers: Paper I (J. Org. Chem. 2010, 75, 7112-7128) deals with the synthesis of 2',4'-propylene-bridged (Carba-ENA) thymidine and its analogues. These carba-ENA nucleosides have been subsequently incorporated into 15mer antisense oligodeoxynucleotides (AON), and their affinity toward complementary mRNA and DNA, as well as their nuclease resistance and RNase H recruitment capability have been investigated in comparison with those of the native and ENA counterparts. Paper II (J. Org. Chem. 2012, 77, 6855–6872) illustrates the synthesis of dimethylbicyclo[2.2.1]heptane and a diastereomeric mixture of oxabicyclo[2.2.1]heptanes by the free-radical ring-closure reaction approach. The role of steric factors for different chair- and the boat-like transition states was evaluated involving the 5-exo radical ring closure reaction to a tethered olefin. Paper III (J. Org. Chem. 2012, 77, 9747-9755) shows an unusual strain releasing reaction of 1-mesyloxy-8,7-dimethylbicyclo[2.2.1]heptane by a base-promoted substitution at the chiral C3 followed by spontaneous concerted ring opening involving the most strained C2-C3-C4 bonds (with bond angle 94°) and the C2 bridgehead leading to anti-endo elimination of the C1-mesyloxy group by the conjugate base of adenine or thymine to give two diastereomeric C3'(S) and C3'(R) derivatives of 1-thyminyl and 9-adeninyl cyclohexene, and a mechanistic rational has been formulated. Paper IV (J. Org. Chem. 2014, 79, 7266−7276) focuses on the diastereospecific synthesis of E/Z bicyclo[2.2.1]heptane-7- and oxabicyclo[2.2.1]heptane-8-oximes and their corresponding C-nitroso derivatives. The comparative kinetic and thermodynamic studies of the conversions of the C-nitroso side products to the required oximes have been delineated leading to the synthesis of desmethyl sugar derivatives.

The high-speed clock and data recovery (CDR) circuit is a key building block of modern communication systems with applications spanning a wide range from wireline long-haul networks to chip-to-chip and backplane communications. In this dissertation, our focus is on the modelling, design and analysis of devices and circuits used in this versatile system in CMOS technology. Of these blocks, we have identified the voltage-controlled oscillator (VCO) as an important circuit that contributes to the total noise performance of the CDR. Among different solutions known for this circuit, LC-VCO is acknowledged to have the best phase noise performance, due to the filtering characteristic of the LC tank circuit. We provide details on modelling and characterization of a special type of varactor, the accumulation-mode MOS varactor, used in the tank circuit as a tuning component of these types of VCOs. We propose a new sub-circuit model for this type of varactor, which can be easily migrated to other technologies as long as an accurate model exists for MOS transistors. The model is suitable whenever the numerical models have convergence problems and/or are not defined for the specific designs (e.g., minimum length structures). The model is verified directly using measurement in a standard CMOS 0.13µm process, and indirectly by comparing the tuning curves of an LC-VCO designed in CMOS 0.13µm and 0.18µm processes. Using a varactor, a circuit technique is proposed for designing a narrowband tuneable clock buffer, which can be used in a variety of applications including the CDR system. The buffer automatically adjusts its driving bandwidth to that of the VCO, using the same control voltage that controls the frequency of the VCO. In addition, a detailed analysis of the impact of large output signals on the tuning characteristics of the LC-VCO is performed. It is shown that the oscillation frequency of the VCO deviates from that of an LC tank.

Thesis (M. App. Sc.)--Carleton University, 2003. / Includes bibliographical references (p. 103-105). Also available in electronic format on the Internet.

Thesis (Ph.D.) - University of St Andrews, December 2007.

Thesis (MS)--Montana State University--Bozeman, 2009. / Typescript. Chairperson, Graduate Committee: Brock LaMeres. Includes bibliographical references (leaves 64-66).

Thesis (M. S.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2008. / Committee Chair: Laskar Joy; Committee Member: Cressler John; Committee Member: Tentzeris Emmanouil