Thesis (ME--Engineering) -- AUT University, 2009. / Includes bibliographical references. Also held in print (131 leaves : ill. ; 30 cm. + 1 CD-ROM) in the Archive at the City Campus (T 621.384 PRI)

Thesis (M.A.)--University of Massachusetts Amherst, 2009. / Open access. Includes bibliographical references (p. 144-154).

In the energy-limited wireless sensor node applications, wake-up radios are required to reduce the average power consumption of the node. Energy-detecting receivers are the best fit for such low power operations. This thesis presents the energy-detecting receiver design; challenges; techniques to enhance sensitivity, selectivity; and multi-access operation. Self-mixers instead of the conventional envelope detectors are proposed and proved to be optimal for signal detection. A fully integrated wake-up receiver uses the self-mixer and time-encoded baseband signal processing to provide a sensitivity of -79.1dBm at 434MHz with 420pW of power, providing an 8dB better sensitivity at 10dB lower power consumption compared to the SoA. A novel approach using narrowband interferers as local oscillators will be presented to further enhance sensitivity and selectivity, effectively operating the energy-detector receiver as a direct down-conversion receiver. Additionally, a clockless continuous-time analog correlator will be introduced to enhance the selectivity to wide-band AM interferers. The architecture uses pulse-position-encoded analog signal processing with VCOs as integrators and pulse-controlled relaxation delays; it operates as a code-domain matched filter to de-spread asynchronous wake-up codes. This code-domain matched filtering also provides code-division multiple access (CDMA) for simultaneous wakeups. Additional enhancement in the link can be achieved using directional antennas, providing spatial gain and selectivity. Certain applications can leverage a nearby reflector similar to a Yagi antenna to enhance the directivity. A low power directional backscatter tag is proposed, it uses multiple antennas acting as a reflectarray by configuring constant phase gradients depending on the direction of arrival (DoA) of the signal. Thus, instead of harvesting energy, the same energy and the surrounding environment can be leveraged to enhance functionality (e.g. interferer as LO, using a backscatter tag on a wall) for low power operation. Innovations spanning both system and circuit architectures that leverage the ambient energy and environment to enable power-efficient solutions for next-generation wake-up radios are presented in this work.

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Sensor nodes in a sensor network is power constrained. Transceiver electronics of a node in sensor network consume a good share of total power consumed in the node. The thesis proposes receiver architecture and algorithms which reduces power consumption of the receiver. The work in the thesis ranges from designing low power architecture of the receiver to experimentally verifying the functioning of the receiver. Concepts proposed in the thesis are: Low power adaptive architecture :-A baseband digital receiver design is proposed which changes its sampling frequency and bit-width based on interference detection and SNR estimation. The approach is based on Look-up-table (LUT) in the digital section of the receiver. Interference detector and SNR estimator has been proposed which suits this approach. Settings of different sections of digital receiver changes as sampling frequency and bit-width varies. But, this change in settings ensures that the desired BER is achieved. Overall, the receiver reduces amount of processing when conditions are benign and does more processing when conditions are not favorable. It is shown that the power consumption by the digital baseband can be reduced by 85% (7 times) when there is no interference and SNR is high. Thus the proposed design meets our requirement of low power hardware. The design is coded in Verilog HDL and power and area estimation is done using Synopsys tools. Faster Simulation Methodologies :-Usually physical layer simulations are done on baseband equivalent model of the signal in the receiver chain. Simulating Physical layer algorithms on bandpass signals for BER evaluation is very time consuming. We need to do the bandpass simulations to capture the effect of quantization on bandpass signal in the receiver. We have developed a variance measuring simulation methodology for faster simulation which reduces simulation time by a factor of 10. Low power, Low area, Non-coherent, Non-data-aided joint tracking and acquisition algorithm :-Correlation is a very popular function used particularly in synchronization algorithms in the receivers. But correlation requires usage of multipliers. Multipliers are area and power consuming blocks. A very low power and low area joint tracking and acquisition algorithm is developed. The algorithm does not use any multiplier to synchronize. Even it avoids squaring and adding the signals to achieve non-coherency. Beside the algorithm is non-data-aided as well and does not require ROM to store the sequence. The Algorithm saves area/power of existing similar algorithms by 90%. Experimental setup for performance evaluation of the receiver :-The developed baseband architecture and algorithms are experimentally verified on a wireless test setup. Wireless test setup consists of FPGA board, VSGs, Oscilloscopes, Spectrum analyzer and a discrete component RF board. Packet error and packet loss measurement is done by varying channel conditions. Many practical and interesting issues dealing with wireless test setup infrastructure were encountered and resolved.