Field-Programmable Gate Arrays (FPGAs) are one of the most popular platforms for implementing digital circuits. Their main advantages include the ability to be (re)programmed in the field, a shorter time-to-market, and lower non-recurring engineering costs. This programmability, however, is afforded through a significant amount of additional circuitry, which makes FPGAs significantly slower and less power-efficient compared to Application Specific Integrated Circuits (ASICs). This thesis investigates three aspects of low-power FPGA design: switching activity estimation, switching activity minimization, and low-power FPGA clock network design. In our investigation of switching activity estimation, we compare new and existing techniques to determine which are most appropriate in the context of FPGAs. Specifically, we compare how each technique affects the accuracy of FPGA power models and the ability of power-aware CAD tools to minimize power. We then present a new publicly available activity estimation tool called ACE-2.0 that incorporates the most appropriate techniques. Using activities estimated byACE-2.0, power estimates and power savings were both within 1% of results obtained using simulated activities. Moreover, the new tool was 69 and 7.2 times faster than circuit simulation for combinational and sequential circuits, respectively. In our investigation of switching activity minimization, we propose a technique for reducing power in FPGAs by minimizing unnecessary transitions called glitches. The technique involves adding programmable delay elements at inputs of the logic elements of the FPGA to align the arrival times, thereby preventing new glitches from being generated. On average, the proposed technique eliminates 87% of the glitching, which reduces overall FPGA power by17%. The added circuitry increases the overall FPGA area by 6% and critical-path delay by less than 1%. Finally, in our investigation of low-power FPGA clock networks, we examine the tradeoff between the power consumption of FPGA clock networks and the cost of the constraints they impose on FPGA CAD tools. Specifically, we present a parameterized framework for describing FPGA clock networks, we describe new clock-aware placement techniques, and we perform an empirical study to examine how the clock network parameters affect the overall power consumption of FPGAs. The results show that the techniques used to produce a legal placement can have a significant influence on power and delay. On average, circuits placed using the most effective techniques dissipate 9.9% less energy and were 2.4% faster than circuits placed using the least effective techniques. Moreover, the results show that the architecture of the clock network is also important. On average, FPGAs with an efficient clock network were up to12.5% more energy efficient and 7.2% faster than other FPGAs.

This thesis presents a low-power LDPC decoder design based on speculative scheduling of energy necessary to decode dynamically varying data frame in both block-fading channels and general AWGN channels. A model of a memory-efficient low-power high-throughput multi-rate array LDPC decoder as well as its FPGA implementa- tion results is first presented. Then, I propose a decoding scheme that provides the feature of constant-time decoding and thus facilitates real-time applications where guaranteed data rate is required. It pre-analyzes each received data frame to estimate the maximum number of necessary iterations for frame convergence. The results are then used to dynamically adjust decoder frequency and switch between multiple-voltage levels; thereby energy use is minimized. This is in contrast to the conventional fixed-iteration decoding schemes that operate at a fixed voltage level regardless of the quality of data received. Analysis shows that the proposed decoding scheme is widely applicable for both two-phase message-passing (TPMP) decoding algorithm and turbo decoding message passing (TDMP) decoding algorithm in block fading channels, and it is independent of the specific LDPC decoder architecture. A decoder architecture utilizing our recently published multi-rate decoding architecture for general AWGN channels is also presented. The result of this thesis is a decoder design scheme that provides a judicious trade-off between power consumption and coding gain.

This thesis includes two topics. The first topic is a high speed phase adjustable ROM-less DDFS (Direct Digital Frequency Synthesizer). The second one is a low-power SRAM design. The high speed phase adjustable ROM-less DDFS employs trigonometric quadruple angle formula with the adjustability of phase and frequency. Neither any scaling tables nor error correction tables are required. In order to meet demands of general communication systems, the ROM-less DDFS is aimed at generating the frequencies for IQ channels. A pipelining design is adopted in our design to boost the frequency of the DDFS. The low-power SRAM uses a negative word-line scheme to reduce the leakage current of word-line controlled transistors (WCT). The leakage current increases with the high density of SRAM which might cause reading and writing errors. The negative word-line scheme not only reduces the leakage current as well as the power, but also makes the SRAM operate reliably during read and write cycles.

Design of low power Turbo decoder is one of the key issues in many modern communication systems such as 3 GPP. For the Turbo decoder architecture, the memory for the storage of the branch metric and state metric represents a major part of the entire decoder no matter in silicon area or power dissipation. Therefore, instead of saving the computed branch memory, this thesis adopts an alternative approach by saving the input in order to generate the branch memory on line. Furthermore, a novel design of state metric unit is proposed such that the size of the total state metric can be effectively reduced by a half with slightly overhead of adders/subtractors. For non-recursive systematic encoding applications, the same design methodology can further reduce the number of arithmetic units required in the soft-output calculating module. Our preliminary experimental result shows that the proposed design methodology can achieve 40% and 13% reduction on the gate count and power dissipation respectively.

In this thesis, we present an implementation of a low-power digital signal processor. We design the hardware units and analyze the instruction set for digital signal process applications. Besides, the power consumption issue is considered. We present two solutions to reduce the power consumption. We also discuss the test pattern generations to verify this DSP processor. Finally, the concept of IP design is considered in this design.

With the current trend towards integration and higher data rates, read channel design needs to incorporate significant boost for a wider signal bandwidth. This dissertation explores the analog design problems associated with design of such 'Equalizing Filter' (boost filter) for read channel applications. Specifically, a 330MHz, 5th order Gm-C continuous time lowpass filter with 24dB boost is designed. Existing architectures are found to be unsuitable for low power, wideband and high boost operation. The proposed solution realizes boosting zeros by efficiently combining available transfer functions associated with all nodes of cascaded biquad cells. Further, circuit techniques suitable for high frequency filter design are elaborated such as: application of the Gilbert cell as a variable transconductor and a new Common-Mode-Feedback (CMFB) error amplifier that improves common mode accuracy without compromising on bandwidth or circuit complexity. A prototype is fabricated in a standard 0.35mm CMOS process. Experimental results show -41dB of IM3 for 250mV peak to peak swing with 8.6mW/pole of power dissipation.

The current trends of mobile battery-powered devices make area and power critical design constraints in many applications. It is important that embedded software implementations execute any given task as power efficiently as possible. These tasks often require the computation of transcendental functions (sine, cosine, exponential, logarithm, etc.). The CORDIC algorithm can be used to implement an area-efficient hardware accelerator to assist in the computation of many of these functions while reducing the total energy consumed. This report presents the design and implementation of a fixed-point CORDIC rotator. The CORDIC rotator is used to assist in the computation of IEEE-754 single-precision floating-point exponentials. Power simulation results show the CORDIC-assisted exponent computation consumes 81.42% less energy as compared with the unassisted software solution while adding less than 10% to the gate count of the original system. / text

Field-Programmable Gate Arrays (FPGAs) are one of the most popular platforms for implementing digital circuits. Their main advantages include the ability to be (re)programmed in the field, a shorter time-to-market, and lower non-recurring engineering costs. This programmability, however, is afforded through a significant amount of additional circuitry, which makes FPGAs significantly slower and less power-efficient compared to Application Specific Integrated Circuits (ASICs). This thesis investigates three aspects of low-power FPGA design: switching activity estimation, switching activity minimization, and low-power FPGA clock network design. In our investigation of switching activity estimation, we compare new and existing techniques to determine which are most appropriate in the context of FPGAs. Specifically, we compare how each technique affects the accuracy of FPGA power models and the ability of power-aware CAD tools to minimize power. We then present a new publicly available activity estimation tool called ACE-2.0 that incorporates the most appropriate techniques. Using activities estimated byACE-2.0, power estimates and power savings were both within 1% of results obtained using simulated activities. Moreover, the new tool was 69 and 7.2 times faster than circuit simulation for combinational and sequential circuits, respectively. In our investigation of switching activity minimization, we propose a technique for reducing power in FPGAs by minimizing unnecessary transitions called glitches. The technique involves adding programmable delay elements at inputs of the logic elements of the FPGA to align the arrival times, thereby preventing new glitches from being generated. On average, the proposed technique eliminates 87% of the glitching, which reduces overall FPGA power by17%. The added circuitry increases the overall FPGA area by 6% and critical-path delay by less than 1%. Finally, in our investigation of low-power FPGA clock networks, we examine the tradeoff between the power consumption of FPGA clock networks and the cost of the constraints they impose on FPGA CAD tools. Specifically, we present a parameterized framework for describing FPGA clock networks, we describe new clock-aware placement techniques, and we perform an empirical study to examine how the clock network parameters affect the overall power consumption of FPGAs. The results show that the techniques used to produce a legal placement can have a significant influence on power and delay. On average, circuits placed using the most effective techniques dissipate 9.9% less energy and were 2.4% faster than circuits placed using the least effective techniques. Moreover, the results show that the architecture of the clock network is also important. On average, FPGAs with an efficient clock network were up to12.5% more energy efficient and 7.2% faster than other FPGAs.

Animal monitoring devices are deployed by the Department of Conservation (DOC) in remote areas. Currently this requires field workers to visit each device on a regular basis, which is costly and time consuming. This report details wireless technologies that would allow remote monitoring of these devices to bring about increased operational efficiency for DOC. Of particular interest is the wireless transmission of images through forested terrain. While traditionally recognised as a difficult environment for wireless communications, research undertaken has indicated transmissions at 27 MHz are capable of achieving the feat. Development of a working system is greatly reduced through the use of Slow Scan Television technology; however justification for the system requires further study into particular case studies.

Field-Programmable Gate Arrays (FPGAs) are one of the most popular platforms for implementing digital circuits. Their main advantages include the ability to be (re)programmed in the field, a shorter time-to-market, and lower non-recurring engineering costs. This programmability, however, is afforded through a significant amount of additional circuitry, which makes FPGAs significantly slower and less power-efficient compared to Application Specific Integrated Circuits (ASICs). This thesis investigates three aspects of low-power FPGA design: switching activity estimation, switching activity minimization, and low-power FPGA clock network design. In our investigation of switching activity estimation, we compare new and existing techniques to determine which are most appropriate in the context of FPGAs. Specifically, we compare how each technique affects the accuracy of FPGA power models and the ability of power-aware CAD tools to minimize power. We then present a new publicly available activity estimation tool called ACE-2.0 that incorporates the most appropriate techniques. Using activities estimated byACE-2.0, power estimates and power savings were both within 1% of results obtained using simulated activities. Moreover, the new tool was 69 and 7.2 times faster than circuit simulation for combinational and sequential circuits, respectively. In our investigation of switching activity minimization, we propose a technique for reducing power in FPGAs by minimizing unnecessary transitions called glitches. The technique involves adding programmable delay elements at inputs of the logic elements of the FPGA to align the arrival times, thereby preventing new glitches from being generated. On average, the proposed technique eliminates 87% of the glitching, which reduces overall FPGA power by17%. The added circuitry increases the overall FPGA area by 6% and critical-path delay by less than 1%. Finally, in our investigation of low-power FPGA clock networks, we examine the tradeoff between the power consumption of FPGA clock networks and the cost of the constraints they impose on FPGA CAD tools. Specifically, we present a parameterized framework for describing FPGA clock networks, we describe new clock-aware placement techniques, and we perform an empirical study to examine how the clock network parameters affect the overall power consumption of FPGAs. The results show that the techniques used to produce a legal placement can have a significant influence on power and delay. On average, circuits placed using the most effective techniques dissipate 9.9% less energy and were 2.4% faster than circuits placed using the least effective techniques. Moreover, the results show that the architecture of the clock network is also important. On average, FPGAs with an efficient clock network were up to12.5% more energy efficient and 7.2% faster than other FPGAs. / Applied Science, Faculty of / Electrical and Computer Engineering, Department of / Graduate