Qian, Zaichen. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2010. / Includes bibliographical references (leaves 62-67). / Abstracts in English and Chinese. / Abstract --- p.i / Acknowledgement --- p.iii / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- VLSI Design Methodology --- p.1 / Chapter 1.2 --- Low Power Design --- p.6 / Chapter 1.3 --- Literature Review on Multiple Supply Voltage (MSV) --- p.10 / Chapter 1.3.1 --- Voltage Island Partitioning Problems --- p.11 / Chapter 1.3.2 --- Multiple Voltage Assignment (MVA) Problem --- p.12 / Chapter 1.4 --- Literature Review on Dynamic Voltage Scaling and Dynamic Power Management --- p.15 / Chapter 1.4.1 --- Dynamic Voltage Scaling (DVS) Problem --- p.16 / Chapter 1.4.2 --- Dynamic Power Management --- p.20 / Chapter 1.5 --- Thesis Contribution and Organization --- p.22 / Chapter 2 --- Multi-Voltage Floorplan Design --- p.24 / Chapter 2.1 --- Introduction --- p.24 / Chapter 2.2 --- Problem Formulation --- p.26 / Chapter 2.3 --- A Value-Oriented Branch-and-Bound Algorithm --- p.29 / Chapter 2.3.1 --- Branching Rules --- p.30 / Chapter 2.3.2 --- Upper Bounds --- p.31 / Chapter 2.3.3 --- Lower Bounds --- p.32 / Chapter 2.3.4 --- Pruning Rules and Value-Oriented Searching Rules --- p.33 / Chapter 2.4 --- Floorplanning --- p.35 / Chapter 2.5 --- Experimental Results --- p.36 / Chapter 2.5.1 --- Optimal Voltage Assignment --- p.37 / Chapter 2.5.2 --- Floorplanning Results --- p.38 / Chapter 3 --- Low Power Scheduling at System Level --- p.40 / Chapter 3.1 --- Introduction --- p.40 / Chapter 3.2 --- Problem Formulation --- p.42 / Chapter 3.3 --- An Optimal Offline Algorithm --- p.43 / Chapter 3.4 --- Online Algorithm --- p.46 / Chapter 3.4.1 --- Analysis on One Single Interval --- p.46 / Chapter 3.4.2 --- Online Algorithm --- p.49 / Chapter 3.4.3 --- Analysis of the Online Algorithm --- p.52 / Chapter 3.5 --- Experimental Results --- p.56 / Chapter 4 --- Conclusion and Future Work --- p.60 / Bibliography --- p.67

Jiang, Mingqi. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2009. / Includes bibliographical references (leaves [49]-51). / Abstract also in Chinese. / Abstract --- p.i / Acknowledgement --- p.iii / Chapter 1 --- Introduction --- p.1 / Chapter 2 --- Rewiring Background --- p.4 / Chapter 2.1 --- REWIRE --- p.6 / Chapter 2.2 --- GBAW --- p.7 / Chapter 3 --- Retiming --- p.9 / Chapter 3.1 --- Min-Clock Period Retiming --- p.9 / Chapter 3.2 --- Min-Area Retiming --- p.17 / Chapter 3.3 --- Retiming for Low Power --- p.18 / Chapter 3.4 --- Retiming with Interconnect Delay --- p.22 / Chapter 4 --- Rewired Retiming for Flip-flop Reduction --- p.26 / Chapter 4.1 --- Motivation and Problem Formulation --- p.26 / Chapter 4.2 --- Retiming Indication --- p.29 / Chapter 4.3 --- Target Wire Selection --- p.31 / Chapter 4.4 --- Incremental Placement Update --- p.33 / Chapter 4.5 --- Optimization Flow --- p.36 / Chapter 4.6 --- Experimental Results --- p.38 / Chapter 5 --- Power Analysis for Rewired Retiming --- p.41 / Chapter 5.1 --- Power Model --- p.41 / Chapter 5.2 --- Experimental Results --- p.44 / Chapter 6 --- Conclusion --- p.47 / Bibliography --- p.50

Mok, King Keung. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2007. / Includes bibliographical references (leaves 77-79). / Abstracts in English and Chinese. / Abstract --- p.1 / Contents --- p.5 / List of Figures --- p.7 / List of Tables --- p.10 / Acknowledgments --- p.11 / Chapter 1. --- Introduction --- p.12 / Chapter 1.1. --- Low Power Design --- p.12 / Chapter 1.2. --- Power Consumption in Conventional CMOS Logic --- p.13 / Chapter 1.2.1. --- Dynamic Power --- p.13 / Chapter 1.2.2. --- Short-Circuit Power --- p.15 / Chapter 1.2.3. --- Leakage Power --- p.17 / Chapter 1.2.4. --- Static Power --- p.19 / Chapter 1.3. --- Smart Card / RFID --- p.21 / Chapter 1.3.1. --- Applications --- p.21 / Chapter 1.3.2. --- Operating Principle --- p.22 / Chapter 1.3.3. --- Conventional Architecture --- p.23 / Chapter 2. --- Adiabatic Logic --- p.25 / Chapter 2.1. --- Adiabatic Switching --- p.25 / Chapter 2.2. --- Energy Recovery --- p.27 / Chapter 2.3. --- Adiabatic Quasi-Static CMOS Logic --- p.29 / Chapter 2.3.1. --- Logic Structure --- p.29 / Chapter 2.3.2. --- Clocking Scheme --- p.31 / Chapter 2.3.3. --- Flip-flop --- p.33 / Chapter 2.3.4. --- Layout Techniques --- p.38 / Chapter 3. --- Adiabatic RFID --- p.41 / Chapter 3.1. --- System Architecture --- p.41 / Chapter 3.2. --- Circuit Design --- p.42 / Chapter 3.2.1. --- Voltage Limiter --- p.43 / Chapter 3.2.2. --- Substrate Bias Generation Circuit --- p.45 / Chapter 3.2.3. --- Ring Oscillator --- p.46 / Chapter 3.2.4. --- ROM and Control Logic --- p.48 / Chapter 3.2.5. --- Load Modulator --- p.52 / Chapter 3.2.6. --- Experimental Results --- p.53 / Chapter 4. --- Adiabatic Smart Card --- p.59 / Chapter 4.1. --- System Architecture --- p.59 / Chapter 4.2. --- Circuit Design --- p.61 / Chapter 4.2.1. --- ASK Demodulator --- p.61 / Chapter 4.2.2. --- Clock Recovery Circuit --- p.63 / Chapter 4.3. --- Experimental Results --- p.67 / Chapter 5. --- Conclusion --- p.74 / Chapter 6. --- Future Works --- p.76 / Reference --- p.77 / Appendix --- p.80

The advance of digital IC technology has been very fast, as shown by rapid development of DSP, digital communication and digital VLSI. Within electronic signal processing, analog-to-digital conversion is a key function, which converts the analog signal into digital form for further processing. Recently, low-voltage and low-power have become also an important factors in IC development. This thesis investigates some novel techniques for the design of low-power high-performance A/D converters in CMOS technology, and the non-ideal switched-capacitor effects of (SC) circuits. A new successive-approximation A/D converter is proposed with a novel error cancellation scheme. This A/D converter needs only a simple opamp, a comparator, and a few switches and capacitors. It can achieve high resolution with relative low power consumption. A new ratio-independent cyclic A/D converter is also proposed with techniques to compensate for the non-ideal effects. The implementation include a new differential sampling that is used to achieve ratio-independent multiple-by-two operation. Extensive simulations were performed to demonstrate the excellent performance of these data converters. / Graduation date: 1999

Minimizing the dynamic power consumption of a circuit is becoming a more and more important issue for digital circuit design in the age of portable electronics. Among all the arithmetic circuits, addition is the most fundamental operation. Therefore, designing low power adder is an important and necessary research area. In this thesis, the dynamic switching power consumption of ripple carry adder, carry look ahead adder, carry skip adder, carry select adder, and prefix adder are discussed. The power factor, the sum of products of probability and fan-out of all internal nodes, is presented. This thesis also studies the power and time trade-off with efficiency index which is the product of power factor and worst case gate counts. The result shows that the carry look ahead adder has the lowest efficiency index in the design of a 64 bit adder. The carry skip adder is the best one in a design of a 16 and 32 bit adder. The ripple carry adder is the best choice for an 8 bit adder. This study also presents a low power prefix adder design which will reduce the power consumption of the prefix adder without lost of performance. / Graduation date: 1998

Thesis (M.S.)--Oregon State University, 2007. / Printout. Includes bibliographical references (leaves 82-86). Also available on the World Wide Web.

No description available.

Thesis (M.S.)--University of Missouri-Columbia, 2003. / Typescript. Includes bibliographical references (leaves 132-133). Also available on the Internet.

Thesis (M.S.)--University of Missouri-Columbia, 2003. / Typescript. Includes bibliographical references (leaves 132-133). Also available on the Internet.

Thesis (Ph. D.)--School of Electrical and Computer Engineering, Georgia Institute of Technology, 2004. Directed by Abhijit Chatterjee. / Vita. Includes bibliographical references (leaves 127-145).