Laboratory source is basic and necessary part of almost every modern electronics laboratories. Development cannot be done without good laboratory resources. It is main function is supply stabilized DC voltage and current. It appears in a simpler version without the continuous regulation of voltage and current, with only predetermined switching voltage. Of course there are also more demanding applications, where stable voltage adjustable fluently and where is continuous of stable voltage for example LCD applications. This term project deals with a connection of microprocessor and stabilizing and regulating circuits for voltage and current of laboratory sources output. That microprocessor controls performance features by DA converter, which provide a stable output voltage which required power.

The aim of master thesis was to investigate a simple camera and processor Atmel AVR unit implementation. Thesis describes how to get image from C3088 module and management over the bank of camera registers. Work includes limitation draft for this way of processing the information. Thesis also solves an exemplary model for object recognition using this implementation.

The task of my thesis was to automate the process of 3D stacking. The work includes design of complex control board, that will serve as a control unit and provide a comprehensive function of mechanical displacement in combination with digital image acquisition. In addition, the electronics for controlling a stepper motor, PCB and the design. The result of this is a facility that provides automatic acquisition of images with different depth of field.

This thesis describes the design of construction of the converter USB joystick on the Ethernet interface. In the first part are theoretically analyzed both protocols used for the converter. An analysis of current microprocessor trade and their possible using for application in this project. Next part including the specification of used microprocessor and all options of programming and debugging of the microprocessor. Another part deals with the detailed design of the hardware interface. The last part describes the software equipment of microprocessor and the final appreaciation of work.

This work deals with the creation and construction of universal microprocessor controller on ARM7TDMI architecture. There are described various hardware features of this controller, design of the device, software equipment, used control algorithms and their implementation into the AT91SAM7X512 microcontroller. There is also described the verification of the controller on real plant.

The thesis deals with design of the device for monitoring four signals from the probes for scanning ECG, PPG and heart pressure. The thesis is mainly focused on hardware design of the device and the most important part is the selection of the storage media to which will be the data recorded and the selection of the microprocessor which has to be able to meet the requirements of the device. For the data recording is used SD card and the ARM based MCU was selected from the AT91SAM7S series. This thesis also deals with the software design for MCU which is needed to launch the device and with design of PC applications used for setting the device and for downloading the measured data. At the end there are presented results of the constructed device.

In the context of this master’s thesis are solved algorithms and hardware for control BLDC motor. The first was designed algorithm in LabView called "six-step". This algorithm causes a torque ripple, so in the final version was used vector control. It is a sensor control, so was necessary to design a measurement of rotor position. It was solved using a magnetic position sensor. After testing the control algorithm was designed my own hardware for control the BLDC motor. The main control unit was chosen microprocessor MC56F82743, which is designed specifically for BLDC motor control. The microprocessor was programmed in the CodeWarrior development environment, using a JTAF and USB-TAP.

The goal of this thesis is create measuring station of resolver with using Analog Devices AD2S1210. The measuring station is based on the Atmel ATmega16 microprocesor and programmed in the C language. The measuring plant of resolvers to detection fault per one revolution is developed with industrial cooperation. The measuring station is made for a mobile use with onboard Pb accu. Measuring station will be used as a service device or in the manufacturing for setting the right angle of resolver on the engine. For the faults debugging of resolvers cables and other faults with the signal chain between the resolver and AD2S1210 is possible to show the SIN and COS signals on the external scope.

The partitioning of complex processor models on the gate and register-transfer level for parallel functional simulation based on the clock-cycle algorithm is considered. We introduce a hierarchical partitioning scheme combining various partitioning algorithms in the frame of a competing strategy. Melting together the di®erent partitioning results within one level using superpositions we crossover to a mixture of experts one. This approach is improved applying genetic algorithms. We present two new partitioning algorithms (experts), the Backward-Cone-Concentration algorithm (n-BCC) and the Minimum-Overlap Cone-Cluster algorithm (MOCC), both of them taking cones as fundamental units for building partitions.

El funcionamiento correcto de un sistema electrónico, aún bajo perturbaciones y fallos causados por la radiación, ha sido siempre un factor crucial en aplicaciones aeroespaciales, médicas, nucleares, de defensa, y de transporte. La tolerancia de estos sistemas, o de los componentes que los integran, a fallos de tipo Single Event Effects (SEEs), es un tema de investigación importante y una característica imprescindible de cualquier sistema utilizado, no solo en aplicaciones críticas, sino también en las aplicaciones del día a día. Por esta razón, las aplicaciones de estos sistemas requieren, cada vez más, herramientas, métricas y parámetros específicos que permitan evaluar la tolerancia a fallos; y a su vez, permitan guiar el proceso para aplicar de forma eficiente los mecanismos de protección utilizados para la mitigación de estos fallos. En este contexto, esta tesis doctoral presenta una herramienta de inyección de fallos y la metodología para la realización de campañas de inyección de fallos tipo Single Event upset (SEU) en procesadores Commercial Off-The-Shelf (COTS) y a través de plataformas de emulación/simulación. Esta herramienta aprovecha las ventajas que ofrecen las infraestructuras de depuración de hardware tales como On-Chip Debugging (OCD), y el depurador estándar de GNU (GDB) para la ejecución y depuración de los casos de estudio. También, se analiza la posibilidad de utilizar un modelo descrito en HDL (Hardware Description Language) del procesador MSP430 de Texas Instruments para estimar la fiabilidad de las aplicaciones al principio de la fase de desarrollo. Se utilizan diferentes métodos de inyección de fallos que muestran las ventajas que ofrece la emulación FPGA en comparación con las campañas de inyección llevadas a cabo en los dispositivos reales. La vulnerabilidad del banco de registros se compara y analiza por cada uno de sus registros. Por otro lado, esta memoria de tesis presenta una métrica para la aplicación eficiente del endurecimiento selectivo basada en software, que hemos llamado SHARC (Software based HARdening Criticality). Adicionalmente, también presenta un método para guiar el proceso de endurecimiento según la clasificación generada por la métrica SHARC. De esta forma, se logra proteger los recursos internos del procesador, obteniendo una cobertura máxima de fallos con los mínimos sobrecostes de protección (overheads). Esto permite diseñar sistemas confiables a bajo coste, logrando obtener un punto óptimo entre los requisitos de confiabilidad y las restricciones de diseño, evitando el uso excesivo de costosos mecanismos de protección (hardware y software).