It is well known that microprocessor performance can be improved by lowering the junction temperature. Two stage cascaded vapor compression refrigeration (VCR) is a mature, inexpensive, and reliable cooling technology that can offer chip temperatures down to ?? C. Recent studies have shown that for a power limited computer chip, there is a non-linear scaling effect that offers a 4.3X performance enhancement at ?? C. The heat transfer performance of a compact evaporator is often the bottleneck in sub-ambient heat removal. For this reason, the design of a deep sub-ambient compact evaporator is critical to the cooling system performance and has not been addressed in the literature. Four compact evaporator designs were investigated as feasible designs - a baseline case with no enhancement structures, micro channels, inline pin fin arrays, and alternating pin fin arrays. A parametric experimental investigation of four compact evaporator designs has been performed aiming at enhancing heat transfer. Each evaporator consists of oxygen free copper and has a footprint of 20 mm x 36 mm, with a total thickness of 3.1 mm. The micro channel evaporator contains 13 channels that are 400 um wide by 1.2 mm deep, and the pin fin evaporators contain approximately 80 pin fins that are 400 um wide by 1.2 mm tall with a pitch of 800 um. Two phase convective boiling of R508b refrigerant was investigated in each evaporator at flow rates of 50 - 70 g/min and saturation temperatures of ??to ??C. Pressure drop and local heat transfer measurements are reported and used to explain the performance of the various evaporator geometries. The results are compared to predictions from popular macro- and micro-channel heat transfer and pressure drop correlations. The challenges of implementing a two stage cascade VCR systems for microprocessor refrigeration are also discussed.

In the present task it is analysed the influence of centralist microprocessor traffic control system for Kaišiadorys – Radviliškis track capasity and traffic safety. It is given a lot of attention to description of the system, infrastructure reconstruction and calculations of the track Kaišiadorys – Radviliškis capasity. In the task it is given the evaluation of Kaišiadorys – Radviliškis track capasity and traffic safety. It is explored the track eploitation problems and perspectives. JSC Lietuvos geležinkeliai could use the calculation results of track capasity and intervals making trains traffic timetables, the calculations and suggestions also could be used making the exploitation plans for I and IX corridors development.

Sistemas embarcados estão mais complexos e são cada vez mais utilizados em contextos que exigem muitos recursos computacionais. Isso significa que o hardware embarcado pode ser composto por vários processadores, memórias, partes reconfiguráveis e ASIPs integrados em um único silício. Adicionalmente, o software embarcados pode conter muitas rotinas de programação executadas sob restrição de processamento e memória. Esse cenário estabelece uma forte dependência entre o hardware e o software embarcado. Portanto, o teste de um sistema embarcado compreende o teste do hardware e do software. Neste contexto, a reutilização de procedimentos e estruturas de teste é um caminho para se reduzir o tempo de desenvolvimento e execução dos testes. Neste trabalho é apresentado um método de teste integrado de hardware e software. Nesse método, casos de teste desenvolvidos para testar o software embarcado também são usados para testar o seu processador. Comparou-se os custos e cobertura de falhas do método proposto com técnicas de auto-teste funcional. Os resultados experimentais demonstraram que foi possível reduzir os custos de aplicação e geração do teste do sistema usando um método de teste integrado de software e hardware. / Embedded Systems are more complexity. Nowadays, they are used in context that requires computational resources. This means an embedded hardware may be compound of several processors, memories, reconfigurable parts, and ASICs integrated in a single die. Additionally, an embedded software has a lot of programming procedures, which is under processing and memory constraints. This scenario provides a stronger connection between hardware and software. Therefore, the test of an embedded system is the test of both, hardware and software. In this context, reuse of testing structures and procedures is one way to reduce the test development time and execution. This work presents an integrated test of software and software method. In this method, test cases developed to test the embedded software are also used to test its processor. We compared the costs and fault coverage of our proposed method with techniques of functional self-test. The experimental results show that it is possible to reduce the implementation and test generation costs using an integrated test of software and hardware.

Sistemas embarcados estão mais complexos e são cada vez mais utilizados em contextos que exigem muitos recursos computacionais. Isso significa que o hardware embarcado pode ser composto por vários processadores, memórias, partes reconfiguráveis e ASIPs integrados em um único silício. Adicionalmente, o software embarcados pode conter muitas rotinas de programação executadas sob restrição de processamento e memória. Esse cenário estabelece uma forte dependência entre o hardware e o software embarcado. Portanto, o teste de um sistema embarcado compreende o teste do hardware e do software. Neste contexto, a reutilização de procedimentos e estruturas de teste é um caminho para se reduzir o tempo de desenvolvimento e execução dos testes. Neste trabalho é apresentado um método de teste integrado de hardware e software. Nesse método, casos de teste desenvolvidos para testar o software embarcado também são usados para testar o seu processador. Comparou-se os custos e cobertura de falhas do método proposto com técnicas de auto-teste funcional. Os resultados experimentais demonstraram que foi possível reduzir os custos de aplicação e geração do teste do sistema usando um método de teste integrado de software e hardware. / Embedded Systems are more complexity. Nowadays, they are used in context that requires computational resources. This means an embedded hardware may be compound of several processors, memories, reconfigurable parts, and ASICs integrated in a single die. Additionally, an embedded software has a lot of programming procedures, which is under processing and memory constraints. This scenario provides a stronger connection between hardware and software. Therefore, the test of an embedded system is the test of both, hardware and software. In this context, reuse of testing structures and procedures is one way to reduce the test development time and execution. This work presents an integrated test of software and software method. In this method, test cases developed to test the embedded software are also used to test its processor. We compared the costs and fault coverage of our proposed method with techniques of functional self-test. The experimental results show that it is possible to reduce the implementation and test generation costs using an integrated test of software and hardware.

Este trabalho descreve o projeto, a construção e a avaliação de um digitalizador de sinais controlado por microprocessador, desenvolvido para ser utilizado em Tomografia por Ressonância Magnética Nuclear, TORM. O digitalizador apresenta dois canais de entrada com digitalização simultânea em 256, 512 ou 1024 palavras por canal e com taxa de amostragem máxima de 22,7 Khz. A resolução é de 12 bits com conversão analógico/digital por aproximação sucessiva. Não há controles manuais o que exige um computador hospedeiro para o ajuste de parâmetros via interface de comunicação paralela destinada para este fim. Opcionalmente pode-se utilizar uma interface serial do tipo RS232C-EIA operando com velocidade máxima de 9600 bauds. O equipamento efetua o processamento local da média acumulativa do sinal, técnica empregada para melhorar a relação sinal/ruído no caso de ruído aleatório. Um circuito dedicado à monitoração permite que se visualize em monitor X-Y tanto o sinal como a sua média. No caso da média, por ela ser acumulativa, há um ajuste automático de escala / This work describes the design, construction and evaluation of a microprocessor controlled digitizer developed to be used in Magnetic Resonance Tomography or Imaging, MRI. The digitizer presents two input channels with simultaneous digitalization in 256, 512 or 1024 words per channel with a sample rate up to 22.7 Khz. A resolution of 12 bits is obtained with successive approximation A/D conversion. There are no manual controls. So a host computer is needed to adjust the parameters through a parallel communication interface available for this purpose. Optionally, a RS232-EIA type serial interface may be used, operating at speeds up to 9600 bauds. Signal average can be processed locally by the equipment. This technique is used to improve the signal to noise ratio in case of random noise. A dedicated circuit permits the visualization of the signal and or its average on an x-y monitor. To monitor cumulative averaged data an automatic scale adjustment is provided

De nombreux microprocesseurs modernes mettent en œuvre le multi-threading simultané (SMT) pour améliorer l'efficacité globale des processeurs superscalaires. SMT masque les opérations à longue latence en exécutant les instructions de plusieurs threads simultanément. Lorsque les threads exécutent le même programme (cas des applications SPMD), les mêmes instructions sont souvent exécutées avec des entrées différentes. Les architectures SMT traditionnelles exploitent le parallélisme entre threads, ainsi que du parallélisme de données explicite au travers d'unités d'exécution SIMD. L'exécution SIMD est efficace en énergie car le nombre total d'instructions nécessaire pour exécuter un programme est significativement réduit. Cette réduction du nombre d'instructions est fonction de la largeur des unités SIMD et de l'efficacité de la vectorisation. L'efficacité de la vectorisation est cependant souvent limitée en pratique. Dans cette thèse, nous proposons l'architecture de vectorisation dynamique inter-thread (DITVA) pour tirer parti du parallélisme de données implicite des applications SPMD en assemblant dynamiquement des instructions vectorielles à l'exécution. DITVA augmente un processeur à exécution dans l'ordre doté d'unités SIMD en lui ajoutant un mode d'exécution vectorisant entre threads. Lorsque les threads exécutent les mêmes instructions simultanément, DITVA vectorise dynamiquement ces instructions pour assembler des instructions SIMD entre threads. Les threads synchronisés sur le même chemin d'exécution partagent le même flot d'instructions. Pour conserver du parallélisme de threads, DITVA groupe de manière statique les threads en warps ordonnancés indépendamment. DITVA tire parti des unités SIMD existantes et maintient la compatibilité binaire avec les architectures CPU existantes. / Many modern microprocessors implement Simultaneous Multi-Threading (SMT) to improve the overall efficiency of superscalar CPU. SMT hides long latency operations by executing instructions from multiple threads simultaneously. SMT may execute threads of different processes, threads of the same processes or any combination of them. When the threads are from the same process, they often execute the same instructions with different data most of the time, especially in the case of Single-Program Multiple Data (SPMD) applications.Traditional SMT architecture exploit thread-level parallelism and with the use of SIMD execution units, they also support explicit data-level parallelism. SIMD execution is power efficient as the total number of instructions required to execute a complete program is significantly reduced. This instruction reduction is a factor of the width of SIMD execution units and the vectorization efficiency. Static vectorization efficiency depends on the programmer skill and the compiler. Often, the programs are not optimized for vectorization and hence it results in inefficient static vectorization by the compiler.In this thesis, we propose the Dynamic Inter-Thread vectorization Architecture (DITVA) to leverage the implicit data-level parallelism in SPMD applications by assembling dynamic vector instructions at runtime. DITVA optimizes an SIMD-enabled in-order SMT processor with inter-thread vectorization execution mode. When the threads are running in lockstep, similar instructions across threads are dynamically vectorized to form a SIMD instruction. The threads in the convergent paths share an instruction stream. When all the threads are in the convergent path, there is only a single stream of instructions. To optimize the performance in such cases, DITVA statically groups threads into fixed-size independently scheduled warps. DITVA leverages existing SIMD units and maintains binary compatibility with existing CPU architectures.

The Multicore Multithreaded Microprocessor maximizes parallelism on a chip for the optimal system performance, such that its popularity is growing rapidly in high-performance computing. It increases the complexity in resource distribution on a chip by leading it to two directions: isolation and unification. On one hand, multiple cores are implemented to deliver the computation and memory accessing resources to more than one thread at the same time. Nevertheless, it limits the threads’ access to resources in different cores, even if extensively demanded. On the other hand, simultaneous multithreaded architectures unify the domestic execu- tion resources together for concurrently running threads. In such an environment, threads are greatly affected by the inter-thread interference. Moreover, the impacts of the complicated distribution are enlarged by variation in workload behaviors. As a result, the microprocessor requires an adaptive management scheme to schedule threads throughout different cores and coordinate them within cores. In this study, an adaptive thread management scheme was proposed, integrating both hardware and software approaches. The instruction fetch policy at the hardware level took the responsibility by prioritizing domestic threads, while the Operating System scheduler at the software level was used to pair threads dynami- vi cally to multiple cores. The tie between them was the proposed online linear model, which was dynamically constructed for every thread based on data misses by the regression algorithm. Consequently, the hardware part of the proposed scheme proactively granted higher priority to the threads with less predicted long-latency loads, expecting they would better utilize the shared execution resources. Mean- while, the software part was invoked by such a model upon significant changes in the execution phases and paired threads with different demands to the same core to minimize competition on the chip. The proposed scheme was compared to its peer designs and overall 43% speedup was achieved by the integrated approach over the combination of two baseline policies in hardware and software, respectively. The overhead was examined carefully regarding power, area, storage and latency, as well as the relationship between the overhead and the performance.

This diploma thesis deals with design of welding power supply for MIG / MAG and MMA technique with continuous output current 120 A. The first, theoretical part is devoted to welding process technology, physical characteristics of electric arc and description of individual welding methods. The thesis also deals with the concept of power converter. The design of the switched-mode power supply is based on a full bridge topology. In order to implement advanced controls of welding power supply, the ARM Cortex M4 microprocessor was selected. Due to the large power consumption of the stepper motor for drive the welding wire, an auxiliary switched-mode power supply was also implemented. The documentation describing the realization of the welding power supply and the results of the measurements are in the last part of the thesis. The welding power supply was successfully revived and reached nominal parameters. Inert gas welding has not been tested yet, due to lack of time caused by extensive work in order to complete mechanical realization.

In this diploma thesis, universal inverter was manufactured and successfully tested with DC, BLDC and AC motor. Inverter is composed of the power board for driving extralow voltage supplied electric motors (from +12V to +24V) and control board with microcontroller MC56F8257. There is also explained the principle of driving DC, BLDC and AC motor as well as description of the most frequently used peripherals and inverter. components

The first part of the work was dealing in general with switched power supply and types of battery chargers. The second part is made by my own design of microprocessor driven battery charger. The design is based on datasheets and recommended circuit connection. The electrical scheme and also the printed circuit board was designed in Eagle 5.11.0 design system. The battery charger is capable of charging these types of batteries: lead acid, NiMH, NiCd, LiPol a alkaline accumulators, and the maximal output current from charger is 3A. The software implementation and design are also part of this master‘s thesis.