Th. doct.-ing.--Électronique--Grenoble--I.N.P., 1982. N°: DI 282.

Ce travail de thèse traite des différents phénomènes de dégradation que peuvent subir les transistors MOS suivant leurs applications sur les technologies CMOS avec mémoires non-volatiles embarquées. Les transistors MOS pour application aux mémoires non volatiles à stockage de charge qui sont enclins à des mécanismes de dégradation spécifiques liés à l’utilisation de la haute tension, ont été étudiés. De plus, des variations de procédés de fabrication ou d’architectures, peuvent avoir un impact sur les mécanismes de dégradation des transistors MOS. En effet, plusieurs modifications des étapes de fabrication peuvent être apportées dans le but d’améliorer les performances des MOSFETs. Le cas des transistors digitaux pour application faible consommation a été considéré ici avec comme objectif principal d’augmenter la mobilité des porteurs dans le canal des transistors MOS. Aussi, suite à certaines limites de l’architecture conventionnelle des transistors MOS, des études ont été menées sur les transistors analogiques et digitaux présentant de nouvelles architectures ayant pour but la suppression de l’effet « hump » ou la réduction de l’aire totale du transistor en déplaçant le contact de grille au-dessus de la zone active. / This thesis focuses on various degradation phenomena that can impact MOS transistors according to their applications on CMOS technologies with embedded non-volatile memories. The transistors used in order to apply potentials greater than 10V in programming and erasing steps of charge storage non-volatile memories have been studied. These transistors are impacted by specific degradation mechanisms due to the use of high voltage. Moreover, manufacturing processes can be modified in order to improve MOSFETs performances, and thus, these variations may have an impact on the degradation mechanisms of MOS transistors. Therefore, several process steps of digital transistor for low power application were changed in order to increase carrier mobility. Furthermore, due to limitations of MOS transistors conventional architecture, new architectures have been proposed for analog and digital transistors in order to remove the "hump" effect or reduce the total area of transistor by moving the gate contact over active area.

This work demonstrates design of analog circuit blocks using radiation-hardened and temperature tolerant silicon carbide enhancement and depletion JFET. Most of the work to date in silicon carbide is focused on CMOS like circuits, which are less temperature tolerant, compared to JFETs. In this work, efforts have been made to accurately model silicon carbide depletion and enhancement mode n-JFETs. I-V characteristics of the models were simulated for different values of channel thickness and doping concentration. Analog circuit building blocks such as current mirrors and sources are presented for both enhancement mode and depletion mode JFETs at different temperatures. A source coupled differential amplifier was designed using depletion mode silicon carbide n-JFETs. Various differential amplifier specifications such as Voltage swing, input common mode range (ICMR), differential gain, common mode gain and Common mode rejection ratio (CMRR) are simulated at room temperature and at 673K.

Titre de l'écran-titre (visionné le 13 décembre 2023) / Ce mémoire présente le développement d'un système sur puce basé sur un processeur RISC-V dans le but de proposer une solution technologique pouvant être utilisée pour un instrument biomédical mesurant la concentration de neurotransmetteurs par l'utilisation d'une caméra. La solution présentée inclue les interfaces nécessaires au contrôle de cet instrument soit des sorties digitales pour le contrôle de pompes microfluidique et du capteur optique, une interface I2C et SPI pour interfacer la caméra, puis une interface UART pour envoyer le résultat à un système externe. Le système a été testé en simulation pour valider le fonctionnement de l'intégration puis a été implanté sur deux FPGAs, soit le Cyclone IV et le ZCU102. L'implémentation finale du prototype a été faite sur une technologie TSMC CMOS 180 nm. Le système peut fonctionner jusqu'à une fréquence de 37.5 MHz. Cependant, pour la fréquence de fonctionnement cible de 10 MHz, la consommation est de 162 mW. La performance du processeur RISC-V du système mesurée par CoreMark est de 0.58 CM/MHz. Le système d'exploitation Linux, ainsi que le code embarqué de gestion de la caméra, ont été testés sur la puce électronique fabriquée pour confirmer l'utilisabilité du système pour application prévue. Pour faciliter la programmation du système, un outil de programmation automatique a été développé. / This project presents the development of a system on a chip based on a RISC-V processor. In order to provide a technological solution that can be used for a biomedical instrument measuring the concentration of neurotransmitters with a spectrophotometer. The solution presented here includes the required interfaces for controlling this instruments such as digital outputs to control microfluidic pumps and optical sensor. Next the communication interfaces I2C and SPI are included to interface with the camera and a UART interface is used to transfer the results with an external system. The system has been simulated to validate functionality of the integration and was then implemented on two FPGAS (Cyclone IV and ZCU102). The final implementation of the prototype was achieved on a TSMC CMOS 180 nm technology. The system can be clocked up to 37.5 MHz while the target frequency of 10 MHz resulted in a power consumption of 162 mW. The performance of the RISC-V processor measured by the CoreMark benchmark was 0.58 CM/MHz. The Linux operating system, as well as the firmware for camera management, were tested on the IC in order to confirmthe usability of the system for its target use. To facilitate the programming process, an automated programming tool was developped.

Duas ferramentas para modelamento de indutores planares, retangulares e integrados e as equações analíticas implementadas em um software, foram estudadas e analisadas, para determinar qual é a mais apropriada, ou seja, aquela que fornece os resultados mais próximos de medidas experimentais, com menor custo, maior velocidade, etc. Indutores planares integrados apresentam limitações severas em seu uso. As duas principais são: o baixo valor do fator de qualidade, que limita o ganho e a banda nos amplificadores e filtros que os utilizam; e a dificuldade no seu modelamento e na determinação dos parâmetros que os caracterizam. Apesar das dificuldades no uso destes dispositivos, eles são aplicados em diversos sistemas, tais como transceptores que operam em rádio freqüências. Nestes sistemas, indutores são necessários e sua integração é essencial para se obter soluções completamente integradas. As ferramentas estudadas para o modelamento de indutores neste trabalho foram: ASITIC e SONNET. As equações analíticas foram implementadas no MATLAB. A comparação entre as ferramentas e as equações foi feita por meio de cinco indutores construídos e medidos. Os indutores foram fabricados em tecnologia CMOS de 0,35 µm com quatro camadas de metal. Para realizar a correta comparação entre os resultados simulados e as medidas elétricas, reduzindo ao máximo a interferência de elementos parasitas (inclusos pelos pads), os indutores foram inseridos em estruturas de teste. Estruturas de caracterização apropriadas foram também projetadas para permitir a eliminação do efeito das estruturas de teste sobre as medidas. / Two modeling tools for integrated planar square inductors and one software implementing analytical relations, were studied and analyzed, to determine which is the most appropriate, that is, the tools that will supply the closest results to experimental measurements with, lower costs, higher speed, etc. Integrated planar inductors present severe limitations in their use. The two main limitations are: the low value of the quality factor, that affects the gain and the band of amplifiers and filters where they are used; and the difficulty in modeling and determining of their parameters. Inspire of the difficulties in the use of these devices, they are applied in many systems, such as transceivers that operate in radio frequency. In these systems, inductors are necessary and their integration is essential to obtain completely integrated solutions. In this work the studied tools for inductor modeling were: ASITIC and SONNET. The analytical relations were implementing in MATLAB. The comparisons between the tools were made through five implemented and measured inductors. The inductors were fabricated in a CMOS 0.35 µm technology with four metal layers. In order to carry out the correct comparison between the modeled results and the electric measurements, minimizing the interference of pad parasitic elements, the inductors were inserted within appropriate test structures. Characterization structures were also implemented to allow the elimination of the test structure effects on the measurements.

Thèse doctorat : Dispositifs de l'Electronique Intégrée : Ecully, Ecole centrale de Lyon : 2006. / 107 réf.

Thèse doctorat : Dispositifs de l'Electronique Intégrée : Ecully, Ecole centrale de Lyon : 2006. / Titre provenant de l'écran-titre. 107 réf.

D’une part, les fluctuations et le bruit basse fréquence (BF) dans les dispositifs MOS ont été le sujet de recherche intensive durant ces dernières années. Le bruit BF devient une inquiétude majeure pour la réduction continuelle de la dimension des transistors car le bruit 1/f augmente comme l’inverse de la surface des transistors. Le bruit BF et les fluctuations en excès pourraient constituer une limitation sérieuse du fonctionnement des circuits analogiques et numériques. Le bruit 1/f est également d'importance primordiale pour les applications de circuit RF où il provoque le bruit de phase dans les oscillateurs ou les multiplexeurs. Le développement des technologies submicroniques CMOS a conduit à l’observation d’un nouveau type de bruits, i.e. signaux télégraphiques aléatoires (RTS), entrainant de grandes amplitudes de fluctuations à l’heure actuelle, qui peuvent compromettre la fonctionnalité des circuits. D'autre part, la variabilité statistique dans les caractéristiques de transistor est l'un des défis principaux pour les prochaines générations technologiques. La connaissance détaillée des sources de variabilité est extrêmement importante pour la conception et la fabrication des dispositifs résistants à la variabilité. On constate que la dispersion des valeurs de courant de drain des dispositifs n-MOS plutôt petits de la technologie 28 nm est presque deux décades. Cela résulte de l'impact des dopants aléatoires, de la rugosité de bord des lignes et les variations d'épaisseur d'oxyde, qui est plutôt bien compris, ainsi que du rôle du matériau de grille, en poly silicium ou en métal seulement, qui n’a été que récemment étudié dans les simulations. La confirmation et la quantification expérimentales de la contribution du bruit et des fluctuations BF manquent toujours. En outre, l'étude de la variabilité du bruit BF et de sa relation avec les autres facteurs des variations des dispositifs n'a été jamais effectuée. Par conséquent, les défis de recherches et les objectifs de cette thèse sont centrés vers les études des fluctuations basses fréquences et du bruit dans les technologies CMOS 32nm et au-delà. Plus spécifiquement, le bruit BF sera étudié avec trois objectifs : i) la caractérisation détaillée du bruit BF des nouvelles technologies CMOS comportant des grilles avec high-k/métal, des poches de canal etc., ii) le changement des paramètres de bruit BF des différentes technologies et iii) l'impact du bruit BF et des fluctuations RTS en tant que sources de variabilité pour des applications de circuit analogique et numérique. Le premier objectif adressera l'origine des fluctuations de BF dans des dispositifs CMOS en termes de densité de piège et de localisation des défauts dans le diélectrique de grille et avec la longueur du canal pour différentes architectures (poche, canal de germanium, FD-SOI etc.). La deuxième partie considérera la variabilité du bruit BF résultant de la dispersion énorme des sources de bruit de dispositif à dispositif ; ceci sera conduit grâce à des mesures statistiques des caractéristiques de bruit de BF en fonction de la surface des dispositifs et des générations technologiques. Le troisième objective se concentrera sur l'impact du bruit de BF ou des fluctuations RTS sur le fonctionnement des circuits élémentaires (inverseur, cellule SRAM) et considérés en tant que source temporelle de variabilité. Nous allons aborder ces trois questions une après l’autre dans les paragraphes suivants. / Low frequency (LF) noise and fluctuations in MOS devices has been the subject of intensive research during the past years. The LF noise is becoming a major concern for continuously scaled down devices, since the 1/f noise increases as the reciprocal of the device area. Excessive low frequency noise and fluctuations could lead to serious limitation of the functionality of the analog and digital circuits. The 1/f noise is also of paramount importance in RF circuit applications where it gives rise to phase noise in oscillators or multiplexors. The development of submicronic CMOS technologies has led to the onset of new type of noises, i.e. random telegraph signals (RTS), yielding large current fluctuations, which can jeopardize the circuit functionality. However, the statistical variability in the transistor characteristics is one of the major challenges for upcoming technological nodes. The detailed knowledge of variability sources is extremely important for the design and manufacturing of variability resistant devices. Whereas the impact of random dopants, line edge roughness and oxide thickness variations is relatively well understood, the role of the polysilicon or metal gate material has only lately been investigated in simulations and experimental confirmation and quantification of its contribution is still lacking. In addition, the study of LFN variability behavior and maybe its relation with the other factors of device variations has never been done. Therefore, the research challenges and objectives of this thesis are centered towards the studies of low frequency fluctuations and noise in 32 nm CMOS technologies and beyond. More specifically, the objectives of the LF noise investigation is summarized in the following points: i) Detailed LF noise characterization of new CMOS technologies featuring high-κ metal gate stacks, channel pockets etc, ii) change of LF noise parameters from different technologies and iii) impact of LF noise and RTS fluctuations as a variability sources for analog and digital circuits. The first objective addresses the origin of the LF fluctuations in CMOS devices in terms of trap density and defect localization in the gate dielectric and along the channel for various architectures (pocket, Ge channel, FD-SOI etc). The second objective considers the LF noise variability resulting from huge dispersion of noise sources from device to device; this is conducted owing to statistical measurements of LF noise characteristics as a function of device area and technological splits. The third issue is focused on the impact of LF noise or RTS fluctuations on the operation of elementary circuits (inverter, SRAM cell) regarded as temporal variability source.

Duas ferramentas para modelamento de indutores planares, retangulares e integrados e as equações analíticas implementadas em um software, foram estudadas e analisadas, para determinar qual é a mais apropriada, ou seja, aquela que fornece os resultados mais próximos de medidas experimentais, com menor custo, maior velocidade, etc. Indutores planares integrados apresentam limitações severas em seu uso. As duas principais são: o baixo valor do fator de qualidade, que limita o ganho e a banda nos amplificadores e filtros que os utilizam; e a dificuldade no seu modelamento e na determinação dos parâmetros que os caracterizam. Apesar das dificuldades no uso destes dispositivos, eles são aplicados em diversos sistemas, tais como transceptores que operam em rádio freqüências. Nestes sistemas, indutores são necessários e sua integração é essencial para se obter soluções completamente integradas. As ferramentas estudadas para o modelamento de indutores neste trabalho foram: ASITIC e SONNET. As equações analíticas foram implementadas no MATLAB. A comparação entre as ferramentas e as equações foi feita por meio de cinco indutores construídos e medidos. Os indutores foram fabricados em tecnologia CMOS de 0,35 µm com quatro camadas de metal. Para realizar a correta comparação entre os resultados simulados e as medidas elétricas, reduzindo ao máximo a interferência de elementos parasitas (inclusos pelos pads), os indutores foram inseridos em estruturas de teste. Estruturas de caracterização apropriadas foram também projetadas para permitir a eliminação do efeito das estruturas de teste sobre as medidas. / Two modeling tools for integrated planar square inductors and one software implementing analytical relations, were studied and analyzed, to determine which is the most appropriate, that is, the tools that will supply the closest results to experimental measurements with, lower costs, higher speed, etc. Integrated planar inductors present severe limitations in their use. The two main limitations are: the low value of the quality factor, that affects the gain and the band of amplifiers and filters where they are used; and the difficulty in modeling and determining of their parameters. Inspire of the difficulties in the use of these devices, they are applied in many systems, such as transceivers that operate in radio frequency. In these systems, inductors are necessary and their integration is essential to obtain completely integrated solutions. In this work the studied tools for inductor modeling were: ASITIC and SONNET. The analytical relations were implementing in MATLAB. The comparisons between the tools were made through five implemented and measured inductors. The inductors were fabricated in a CMOS 0.35 µm technology with four metal layers. In order to carry out the correct comparison between the modeled results and the electric measurements, minimizing the interference of pad parasitic elements, the inductors were inserted within appropriate test structures. Characterization structures were also implemented to allow the elimination of the test structure effects on the measurements.

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