Aim of this work was, to investigate the preparation of Si NC memories by sputter deposition. The milestones are as follows: - Review of relevant literature. - Development of processes for an ultrathin tunnel-oxide and high quality sputtered SiO2 for use as control-oxide. - Evaluation of methods for the preparation of an oxygen-deficient silicon oxide inter-layer (the precursor of the Si NC layer). - Characterization of deposited films. - Establishment of techniques capable of probing the phase separation of SiOx and the formation of Si NC. - Establishment of annealing conditions compatible with the requirements of current CMOS technology based on experimental results and simulations of Si NC formation. - Preparation Si NC memory capacitors using the developed processes. - Characterization of these devices by suitable techniques. Demonstration of their memory functionality.

Aim of this work was, to investigate the preparation of Si NC memories by sputter deposition. The milestones are as follows: - Review of relevant literature. - Development of processes for an ultrathin tunnel-oxide and high quality sputtered SiO2 for use as control-oxide. - Evaluation of methods for the preparation of an oxygen-deficient silicon oxide inter-layer (the precursor of the Si NC layer). - Characterization of deposited films. - Establishment of techniques capable of probing the phase separation of SiOx and the formation of Si NC. - Establishment of annealing conditions compatible with the requirements of current CMOS technology based on experimental results and simulations of Si NC formation. - Preparation Si NC memory capacitors using the developed processes. - Characterization of these devices by suitable techniques. Demonstration of their memory functionality.

Neste trabalho é estudada a viabilidade de produção de dispositivos eletrônicos baseados em filmes semicondutores de carbeto de silício estequiométrico (a-Si0,5C0,5:H) obtidos por deposição química por vapor assistida por plasma, PECVD. A proposta do projeto envolve a realização de uma série de trabalhos que permitam avaliar as potencialidades do a-SiC:H para a fabricação de dispositivos semicondutores simples. Deste modo, desenvolvemos as principais etapas para a construção de dispositivos, as quais envolveram a dopagem elétrica por diferentes técnicas com a utilização de diferentes elementos dopantes, a corrosão seletiva por plasma e a obtenção um dielétrico apropriado e compatível com a tecnologia do SiC, bem como o desenvolvimento de processos de cristalização, que podem se mostrar fundamentais para melhorar as propriedades dos filmes de a-SiC:H. Com tais processos aprimorados, fabricamos estruturas MOSiC (metal-óxidocarbeto de silício) a partir do SiC cristalizado, utilizando como dielétrico de porta o SiO2 crescido por oxidação térmica (seca e úmida) dos próprios filmes de carbeto de silício cristalizados. Essas estruturas apresentaram o comportamento típico de um capacitor MOS, com regiões de acumulação, depleção e inversão bem definidas em todos os casos. Também fabricamos heterojunções de filmes de SiC tipo-p (como depositado e tratado termicamente) sobre substratos de Si tipo-n, os quais mostraram boas caracterísitcas retificadoras para as heteroestruturas formadas pelo a-SiC:H como-depositado e tratado termicamente a 550ºC. Além do mais, também projetamos, fabricamos, modelamos e caracterizamos transistores de filme fino de a-SiC:H. De acordo com as caracterizações elétricas observamos que podemos controlar a condutividade do canal, embora os dispositivos ainda precisem ser aprimorados para se obter melhores níveis de corrente. Vemos, portanto que, embora ainda tenham que ser aperfeiçoados, foram construídos com sucesso dispositivos eletrônicos semicondutores baseados em filmes de a-Si0,5C0,5:H obtidos por PECVD. / In this work we studied the viability to build devices based on stoichiometric amorphous silicon carbide semiconductor films (a-Si0.5C0.5:H), obtained by plasma enhanced chemical vapor deposition technique. The project proposal involves the realization of a series of studies that evaluate the potentialities of the a-SiC:H for the fabrication of simple semiconductor devices. In this way, we developed the main steps for the devices\' fabrication, which involved electric doping, by different doping techniques using different doping sources, selective plasma etching and the obtention of an appropriate and compatible dielectric for SiC technology. Besides, we performed crystallization processes that were essential to improve the properties of the amorphous films. By establishing the processes steps, we manufactured MOSiC (metal-oxidesilicon carbide) structures starting from crystallized SiC and using SiO2 as the gate dielectric, which was obtained by thermal oxidation (wet and dry) of the crystallized silicon carbide films. All the structures presented a typical MOS capacitor behavior, with accumulation, depletion and inversion regions well-defined in all the cases. We also fabricated heterojunctions formed by p-type SiC films (as-deposited and annealed) on n-type silicon substrates that showed good rectifying characteristics for as-deposited and annealed at 550ºC a-SiC:H films. Moreover, we designed, manufactured, modeled and characterized a-SiC:H thin film transistors. The electric characterization demonstrated that it is possible to control the channel conductivity; however, the devices still need to be improved to obtain better current levels. Although some improvement still need to be made, we built successfully electronic semiconductor devices based on a-Si0.5C0.5:H films obtained at low temperatures by PECVD technique.

Neste trabalho é estudada a viabilidade de produção de dispositivos eletrônicos baseados em filmes semicondutores de carbeto de silício estequiométrico (a-Si0,5C0,5:H) obtidos por deposição química por vapor assistida por plasma, PECVD. A proposta do projeto envolve a realização de uma série de trabalhos que permitam avaliar as potencialidades do a-SiC:H para a fabricação de dispositivos semicondutores simples. Deste modo, desenvolvemos as principais etapas para a construção de dispositivos, as quais envolveram a dopagem elétrica por diferentes técnicas com a utilização de diferentes elementos dopantes, a corrosão seletiva por plasma e a obtenção um dielétrico apropriado e compatível com a tecnologia do SiC, bem como o desenvolvimento de processos de cristalização, que podem se mostrar fundamentais para melhorar as propriedades dos filmes de a-SiC:H. Com tais processos aprimorados, fabricamos estruturas MOSiC (metal-óxidocarbeto de silício) a partir do SiC cristalizado, utilizando como dielétrico de porta o SiO2 crescido por oxidação térmica (seca e úmida) dos próprios filmes de carbeto de silício cristalizados. Essas estruturas apresentaram o comportamento típico de um capacitor MOS, com regiões de acumulação, depleção e inversão bem definidas em todos os casos. Também fabricamos heterojunções de filmes de SiC tipo-p (como depositado e tratado termicamente) sobre substratos de Si tipo-n, os quais mostraram boas caracterísitcas retificadoras para as heteroestruturas formadas pelo a-SiC:H como-depositado e tratado termicamente a 550ºC. Além do mais, também projetamos, fabricamos, modelamos e caracterizamos transistores de filme fino de a-SiC:H. De acordo com as caracterizações elétricas observamos que podemos controlar a condutividade do canal, embora os dispositivos ainda precisem ser aprimorados para se obter melhores níveis de corrente. Vemos, portanto que, embora ainda tenham que ser aperfeiçoados, foram construídos com sucesso dispositivos eletrônicos semicondutores baseados em filmes de a-Si0,5C0,5:H obtidos por PECVD. / In this work we studied the viability to build devices based on stoichiometric amorphous silicon carbide semiconductor films (a-Si0.5C0.5:H), obtained by plasma enhanced chemical vapor deposition technique. The project proposal involves the realization of a series of studies that evaluate the potentialities of the a-SiC:H for the fabrication of simple semiconductor devices. In this way, we developed the main steps for the devices\' fabrication, which involved electric doping, by different doping techniques using different doping sources, selective plasma etching and the obtention of an appropriate and compatible dielectric for SiC technology. Besides, we performed crystallization processes that were essential to improve the properties of the amorphous films. By establishing the processes steps, we manufactured MOSiC (metal-oxidesilicon carbide) structures starting from crystallized SiC and using SiO2 as the gate dielectric, which was obtained by thermal oxidation (wet and dry) of the crystallized silicon carbide films. All the structures presented a typical MOS capacitor behavior, with accumulation, depletion and inversion regions well-defined in all the cases. We also fabricated heterojunctions formed by p-type SiC films (as-deposited and annealed) on n-type silicon substrates that showed good rectifying characteristics for as-deposited and annealed at 550ºC a-SiC:H films. Moreover, we designed, manufactured, modeled and characterized a-SiC:H thin film transistors. The electric characterization demonstrated that it is possible to control the channel conductivity; however, the devices still need to be improved to obtain better current levels. Although some improvement still need to be made, we built successfully electronic semiconductor devices based on a-Si0.5C0.5:H films obtained at low temperatures by PECVD technique.

Silicon is the main material used in electronics. The evolution of power electronics and the need for more power efficient semiconductor devices led silicon to its limits. Silicon carbide is a promising material for electronic applications with a wide band-gap, high critical electric field, high thermal conductivity and saturation velocity. Except from its superiority to silicon, silicon carbide comes with a drawback of about two orders of magnitude more interface traps in the SiC/SiO2 interface compared with silicon. A result of this drawback is a flat-band voltage shift when applying a stress to the gate of MOS capacitors and power MOSFETs. In order to study the pure characteristics of the SiC/SiO2 interface, two stress methods, a current pulse stress and gate voltage upsweep, have been applied on 4H-SiC capacitors with nitrided thermal oxides at room temperature and at higher temperatures. The flat-band voltage recovery was examined. The flat-band voltage could be restored at room temperature with a gate voltage downsweep while a restoration is not needed at higher temperatures. The maximum voltage (initial voltage) and the voltage rate of the downsweep were investigated and higher initial voltages and lower voltage rates showed to lead to better VFB restoration. A 200 millisecond long current pulse stress was implemented and it had almost similar effects as the voltage upsweep which lasts 50 seconds. / Kisel är det viktigaste materialet som används i elektronik. Utvecklingen av kraftelektronik och behovet av mer energieffektiva halvledarkomponenter ledde kisel till sina gränser. Kiselkarbid är ett lovande material för elektroniska applikationer med ett brett bandgap, högt kritiskt elektriskt fält, hög värmeledningsförmåga och hög mättningshastighet. Förutom dess överlägsenhet gentemot kisel, kommer kiselkarbid med en nackdel med cirka två storleksordningar fler gränssnittsfällor i SiC / SiO2-gränssnittet jämfört med kisel. Ett resultat av denna nackdel är en förskjutning av flatbands-spänningen, VFB, när man applicerar en spänning på gaten till MOS-kondensatorer och kraft- MOSFETar. För att studera de rena egenskaperna hos SiC/SiO2-gränssnittet har två spänningsmetoder, en strömpulsstress och ett uppåtriktat gate-spänningssvep, applicerats på 4H-SiC- kondensatorer med nitriderade termiska oxider vid rumstemperatur och vid högre temperaturer. Återställning av VFB undersöktes. VFB kan återställas vid rumstemperatur med ett nedåtriktat gate-spänningssvep medan en återställning inte behövs vid högre temperaturer. Den maximala spänningen (initialspänningem) och svephastigheten för det nedåtriktade svepet undersöktes och högre initialspänningar och lägre svephastigheter visade sig leda till bättre VFB-återställning. En 200 millisekund lång strömpuls-stress implementerades och den hade nästan samma effekter som ett uppåtriktat spänningssvep

NASA missions require innovative power electronics system and component solutions with long life capability, high radiation tolerance, low mass and volume, and high reliability in space environments. Presently vertical double-diffused MOSFETs (VDMOS) are the most widely used power switching device for space power systems. It is proposed that a new lateral double-diffused MOSFET (LDMOS) designed at UCF can offer improvements in total dose and single event radiation hardness, switching performance, development and manufacturing costs, and total mass of power electronics systems. Availability of a hardened fast-switching power MOSFET will allow space-borne power electronics to approach the current level of terrestrial technology, thereby facilitating the use of more modern digital electronic systems in space. It is believed that the use of a p+/p-epi starting material for the LDMOS will offer better hardness against single-event burnout (SEB) and single-event gate rupture (SEGR) when compared to vertical devices fabricated on an n+/n-epi material. By placing a source contact on the bottom-side of the p+ substrate, much of the hole current generated by a heavy ion strike will flow away from the dielectric gate, thereby reducing electrical stress on the gate and decreasing the likelihood of SEGR. Similarly, the device is hardened against SEB by the redirection of hole current away from the base of the device's parasitic bipolar transistor. Total dose hardness is achieved by the use of a standard complementary metal-oxide semiconductor (CMOS) process that has shown proven hardness against total dose radiation effects.