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Performance analysis of different voltage controlled delay lines in a delay-locked loopBautista, Harold H., 1979- 13 August 2012 (has links)
Bus interfaces keep getting faster and thus requiring designers to build custom physical fabrics that are able to delay clock and(or) data, on their transmitter and receivers, in order to properly receive and send data with enough setup and hold times. Delay locked loops (DLLs) have become fundamental building blocks that address such problems. Not only are they present in physical layers in integrated circuits but they also solve the problem of VLSI systems that suffer from clock skew and jitter. This report focuses on the implementation of a standard DLL and three different voltage controlled delay topologies. The different topologies are designed and compared for metrics such as linearity, delay range, and sensitivity to power supply. / text
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A Novel Architecture for Supply-Regulated Voltage-Controlled OscillatorsChakravarty, Anu 15 January 2010 (has links)
No description available.
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