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Les technologies émergentes, telles que les objets connectés et les réseaux sociaux sont en train de changer notre manière d’interagir avec autrui. De par leur large adoption, ces technologies génèrent de plus en plus de données. Alors que la gestion de larges volumes de données fut l’un des sujets majeurs de la dernière décennie, un nouveau défi est apparu récemment : comment tirer profit de données générées en temps réel. Avec la croissance des capacités de mémoires vives, plusieurs fournisseurs services, tel que Facebook, déploient des péta-octets de DRAM afin de garantir un temps d’accès rapide aux données. Néanmoins, les mémoires vives sont volatiles, et nécessitent souvent des mécanismes de tolérance aux pannes coûteux en termes de performance. Ceci crée des compromis entre la performance, la tolérance aux pannes et l’efficacité dans les systèmes de stockage basés sur les mémoires vives. Dans cette thèse, nous commençons, d’une part, par étudier ces compromis : nous identifions les facteurs principaux qui impactent la performance, l’efficacité et la tolérance aux pannes dans les systèmes de stockage en mémoire.Ensuite, nous concevons et implémentons un nouveau mécanisme de réplication basé sur l’accès à la mémoire distante (RDMA). Enfin, nous portons cette technique à un nouveau type de système de stockage : les systèmes de stockage pour streaming. Nous concevons et implémentons des mécanismes de réplication et de tolérance aux pannes efficaces et un impact minimal sur les performances sur le stockage pour streaming. / Emerging technologies such as connected devices and social networking applications are shaping the way we live, work, and interact with each other. These technologies generate increasingly high volumes of data. Dealing with large volumes of data has been an important focus in the last decade, however, today the challenge has shifted from data volume to velocity: How to store, process, and extract value from data generated With the growing capacity of DRAM, service providers largely rely on DRAM-based storage systems to serve their workloads. Because DRAM is volatile, usually, distributed in-memory storage systems rely on expensive durability mechanisms to persist data.This creates trade-offs between performance, durability and efficiency in in-memory storage systems We first study these trade-offs by means of experimental study. We extract the main factors that impact performance and efficiency in in-memory storage systems. Then, we design and implement a new RDMA-based replication mechanism that greatly improves replication efficiency in in-memory storage systems. Finally, we leverage our techniques and apply them to stream storage systems. We design and implement high-performance replication mechanisms for stream storage, while guaranteeing linearizability and durability.

This thesis mainly intends to study and reach some conclusions related to major challenges concerning vocabulary teaching or learning, how vocabulary teaching can be improved, findings obtained from the studies in order to reach that purpose and to what extend the suggested alternative vocabulary techniques are effective. It is also aimed to outline the basic insights of the mind, storage, and retrieval from the literature involving linguistics and language teaching. Based on above mentioned background knowledge, it is also intended to derive some significant conclusions to improve the effectiveness and thus the quality of vocabulary teaching in language instruction. In accordance with the principles of the human memory, how we can alter current vocabulary instruction techniques and activities and what scholars offer language teachers and learners are dealt with in detail. So as to validate and prove the efficiency of suggested techniques and activities, a case study is carried out and findings are discussed at large. Additionally, interviews about vocabulary teaching have been carried out with the involved students and instructors and the obtained data has been evaluated. In the final part of the research, some implications and suggestion related to vocabulary teaching are provided along with the underlying rationale behind them aiming to increase the quality of teaching of lexical items and as a result to increase overall quality of language instruction.

Yes / Cerium (Ce3+) substituted Ni-Co ferrites with composition Ni0.3Co0.7CexFe2−xO4 (x = 0.0–0.20, with step size 0.05) were synthesized by sol-gel method. Face-centered cubic (FCC) spinel structure was revealed by X-ray analysis. The crystalline size was calculated ranging between 17.1 and 18.8 nm, lattice constant showed a decreasing trend with increase of Ce3+ contents, furthermore, X-ray density was calculated between 5.30 and 5.69 g/cm3. The two characteristic spinel ferrites absorption bands were seen around 550 (cm−1) and 415 (cm−1) in Fourier transform infra-red (FTIR) spectroscopy. The microstructural and elemental studies were carried out by field emission transmission electron microscopy (FE-TEM) and energy dispersive X-ray (EDX) respectively, the average particle size was calculated around 21.83 nm. Magnetic studies were per- formed by vibrating sample magnetometer (VSM), which showed that saturation magnetization Ms and remanence Mr decreased with substitution up to x = 0.10 due to small magnetic moment of Ce3+ than Fe3+. The coercivity Hc increased with substitution up to 908.93 Oe at x = 0.05, then it decreased following the trend of anisotropy constant. The dielectric studies exhibited decrease in dielectric parameters with fre- quency due to decreasing polarization in material. The dielectric loss was significantly decreased in material at high frequency. The Cole-Cole interpretation exhibited conduction mechanism being caused by grain boundary density. These attributes of Ce3+ substituted Ni-Co ferrites suggest their possible use in memory storage, switching and high frequency devices like antenna and satellite systems. / The authors would like to acknowledge the Researcher's Supporting Project Number (RSP-2021/269) King Saud University, Riyadh, Saudi Arabia, for their support in this work.

The ever-growing demand for more computing power forces hardware vendors to put an increasing number of multiprocessors into a single server system, which usually exhibits a non-uniform memory access (NUMA). In-memory database systems running on NUMA platforms face several issues such as the increased latency and the decreased bandwidth when accessing remote main memory. To cope with these NUMA-related issues, a DBMS has to allow flexible data partitioning and data placement at runtime. In this demonstration, we present ERIS, our NUMA-aware in-memory storage engine. ERIS uses an adaptive partitioning approach that exploits the topology of the underlying NUMA platform and significantly reduces NUMA-related issues. We demonstrate throughput numbers and hardware performance counter evaluations of ERIS and a NUMA-unaware index for different workloads and configurations. All experiments are conducted on a standard server system as well as on a system consisting of 64 multiprocessors, 512 cores, and 8 TBs main memory.

Pas de résumé en français / It is generally maintained that one of cortex’ functions is the storage of a large number of memories. In this picture, the physical substrate of memories is thought to be realised in pattern and strengths of synaptic connections among cortical neurons. Memory recall is associated with neuronal activity that is shaped by this connectivity. In this framework, active memories are represented by attractors in the space of neural activity. Electrical activity in cortical neurones in vivo exhibits prominent temporal irregularity. A standard way to account for this phenomenon is to postulate that recurrent synaptic excitation and inhibition as well as external inputs are balanced. In the common view, however, these balanced networks do not easily support the coexistence of multiple attractors. This is problematic in view of memory function. Recently, theoretical studies showed that balanced networks with synapses that exhibit short-term plasticity (STP) are able to maintain multiple stable states. In order to investigate whether experimentally obtained synaptic parameters are consistent with model predictions, we developed a new methodology that is capable to quantify both response variability and STP at the same synapse in an integrated and statistically-principled way. This approach yields higher parameter precision than standard procedures and allows for the use of more efficient stimulation protocols. However, the findings with respect to STP parameters do not allow to make conclusive statements about the validity of synaptic theories of balanced working memory. In the second part of this thesis an alternative theory of cortical memory storage is developed. The theory is based on the assumptions that memories are stored in attractor networks, and that memories are not represented by network states differing in their average activity levels, but by micro-states sharing the same global statistics. Different memories differ with respect to their spatial distributions of firing rates. From this the main result is derived: the balanced state is a necessary condition for extensive memory storage. Furthermore, we analytically calculate memory storage capacities of rate neurone networks. Remarkably, it can be shown that crucial properties of neuronal activity and physiology that are consistent with experimental observations are directly predicted by the theory if optimal memory storage capacity is required.

Anti-ferromagnetic interlayer exchange coupling between iron layers in Fe/MgO superlatices have recently been of interest among researchers for its potential application in 3D memory storage in computers (hard drives) and in the research field of spintronics. Thinfilms and bi-layers between the 10-100 ångström range in thicknesses were analyzed for its resistive properties during different conditions. Both mono-layers and superlatices were experimented with.The resistivity of the films was measured with both the four-probe method and the Van der Pauw method. Because of mechanical limitations with respect to the direction of the external magnetic field, the Van der Pauw method had to be used for the superlattice measurements. The collected data from all the measurments of the superlattice suggest that the electric current is not only passing the capping layer of the lattice but did not however show any sign of resisitive properties changing with changing magnetic profile. The resistivity of thesuperlattice was similar to that of the resistivity calculated from data when the external magnetic field was off. The results from this study show for the first time that it is possible to measure the electronic transport within an Fe/MgO superlattice which provides a basis for futher investigations.

This PhD dissertation proposes innovative methodologies to support the designing and the mapping process of embedded systems. Due to the increasing requirements, embedded systems have become quite complex, as they consist of several partially dependent heterogeneous components. Systematic Design Space Exploration (DSE) methodologies are required to support the near-optimal design of embedded systems within the available short time-to-market. In this target domain, the existing DSE approaches either require too much exploration time to find near-optimal designs due to the high number of parameters and the correlations between the parameters of the target domain, or they end up with a less efficient trade-off result in order to find a design within acceptable time. In this dissertation we present an alternative DSE methodology, which is based on systematic creation of scalable and near-optimal DSE frameworks. The frameworks describe all the available options of the exploration space in a finite set of classes. A set of principles is presented which is used in the reusable DSE methodology to create a scalable and near-optimal framework and to efficiently use it to derive scalable and near-optimal design solutions within a Pareto trade-off space. The DSE reusable methodology is applied to several stages of the embedded system design flow to derive scalable and near-optimal methodologies. The first part of the dissertation is dedicated to the development of mapping methodologies for storing large embedded system data arrays in the lower layers of the on-chip background data memory hierarchy, and the second part to the DSE methodologies for the processing part of SW/HW architectures in embedded systems including the foreground memory systems. Existing mapping approaches for the background memory part are either enumerative, symbolic/polyhedral and worst case (heuristics) approximations. The enumerative approaches require too much exploration time, the worst case approximation lead to overestimation of the storage requirements, whereas the symbolic/polytope approaches are scalable and near-optimal for solid and regular iteration spaces. By applying the new reusable DSE methodology, we have developed an intra-signal in-place optimization methodology which is scalable and near-optimal for highly irregular access schemes. Scalable and near-optimal solutions for the different cases of the proposed methodology have been developed for the cases of non-overlapping and overlapping store and load access schemes. To support the proposed methodology, a new representation of the array access schemes, which is appropriate to express the irregular shapes in a scalable and near-optimal way, is presented. A general pattern formulation has been proposed which describes the access scheme in a compact and repetitive way. Pattern operations were developed to combine the patterns in a scalable and near-optimal way under all the potential pattern combination cases, which may exist in the application under study. In the processing oriented part of the dissertation, a DSE methodology is developed for mapping instance of a predefined target application domain onto a partially fixed architecture platform template, which consists of one processor core and several custom hardware accelerators. The DSE methodology consists of uni-directional steps, which are implemented through parametric templates and are applied without costly design iterations. The proposed DSE methodology explores the space by instantiating the steps and propagating design constraints which prune design options following the steps ordering. The result is a final Pareto trade-off curve with the most relevant near-optimal designs. As the scheduling and the assignment are the major tasks of both the foreground and the datapath, near-optimal and scalable techniques are required to support the parametric templates of the proposed DSE methodology. A framework which describes the scheduling and assignment of the scalars into the registers and the scheduling and assignment of the operation into the function units of the data path is developed. Based on the framework, a systematic methodology to arrive at parametric templates for scheduling and assignment techniques which satisfy the target domain constraints is developed. In this way, a scalable parametric template for scheduling and assignment tasks is created, which guarantees near-optimality for the domain under study. The developed template can be used in the Foreground Memory Management step and Data-path mapping step of the overall design flow. For the DSE of the domain under study, near-optimal results are hence achieved through a truly scalable technique. / Η παρούσα διδακτορική διατριβή προτείνει καινοτόμες μεθοδολογίες για τον σχεδιασμό και τη διαδικασία απεικόνισης σε ενσωματωμένα συστημάτα. Λόγω των αυξανόμενων απαιτήσεων, τα ενσωματωμένα συστήματα είναι αρκετά περίπλοκα, καθώς αποτελούνται από πολλά και εν μέρει εξαρτώμενα ετερογενή στοιχεία. Συστηματικές μεθοδολογίες για την εξερεύνηση του χώρου λύσεων (Design Space Exploration – DSE) απαιτούνται σχεδόν βέλτιστες σχεδιάσεις ενσωματωμένων συστημάτων εντός του διαθέσιμου χρονου. Οι υπάρχουσες DSE μεθοδολογίες απαιτούν είτε πάρα πολύ χρόνο εξερεύνησης για να βρουν τους σχεδόν βέλτιστους σχεδιασμούς, λόγω του μεγάλου αριθμού των παραμέτρων και τις συσχετίσεις μεταξύ των παραμέτρων, ή καταλήγουν με ένα λιγότερο βέλτιστο σχέδιο, προκειμένου να βρειθεί ένας σχεδιασμός εντός του διαθέσιμου χρόνου. Στην παρούσα διδακτορική διατριβή παρουσιάζουμε μια εναλλακτική DSE μεθοδολογία, η οποία βασίζεται στη συστηματική δημιουργία επεκτάσιμων και σχεδόν βέλτιστων DSE πλαισίων. Τα πλαίσια περιγράφουν όλες τις διαθέσιμες επιλογές στο χώρο εξερεύνησης με ένα πεπερασμένο σύνολο κατηγοριών. Ένα σύνολο αρχών χρησιμοποιείται στην επαναχρησιμοποιήούμενη DSE μεθοδολογία για να δημιουργήσει ένα επεκτάσιμο και σχεδόν βέλτιστο DSE πλαίσιο και να χρησιμοποιήθεί αποτελεσματικά για να δημιουργήσει επεκτάσιμες και σχεδόν βέλτιστες σχεδιαστικές λύσεις σε ένα Pareto Trade-off χώρο λύσεων. Η DSE μεθοδολογία εφαρμόζεται διάφορα στάδια της σχεδιαστικής ροής για ενσωματωμένα συστήματα και να δημιουργήσει επεκτάσιμες και σχεδόν βέλτιστες μεθοδολογίες. Το πρώτο μέρος της διατριβής είναι αφιερωμένο στην ανάπτυξη των μεθόδων απεικόνισης για την αποθήκευση μεγάλων πινάκων που χρησιμοποιούνται στα ενσωματωμένα συστήματα και αποθηκεύονται στα χαμηλότερα στρώματα της on-chip Background ιεραρχία μνήμης. Το δεύτερο μέρος είναι αφιερωμένο σε DSE μεθοδολογίες για το τμήμα επεξεργασίας σε αρχιτεκτονικές λογισμικού/υλικού σε ενσωματωμένα συστήματα, συμπεριλαμβανομένων των συστημάτων της προσκήνιας (foreground) μνήμης. Υπάρχουσες μεθοδολογίες απεικόνισης για την Background μνήμης είτε εξονυχιστικές, συμβολικές/πολυεδρικές και προσεγγίσεις με βάση τη χειρότερη περίπτωση. Οι εξονυχιστικές απαιτούν πάρα πολύ μεγάλο χρόνο εξερεύνησης, οι προσεγγίσεις οδηγούν σε υπερεκτίμηση των απαιτήσεων αποθήκευσης, ενώ οι συμβολικές είναι επεκτάσιμη και σχεδόν βέλτιστές μονο για τακτικούς χώρους επαναλήψεων. Με την εφαρμογή της προτεινόμενης DSE μεθοδολογίας αναπτύχθηκε μια επεκτάσιμη και σχεδόν βέλτιστη μεθοδολγοία για την εύρεση του αποθηκευτικού μεγέθους για τα δεδομένα ενός πίνακα για άτακτους και για τακτικούς χώρους επαναλήψεων. Προτάθηκε μια νέα αναπαράσταση των προσπελάσεων στη μνήμη, η οποία εκφράζει τα ακανόνιστα σχήματα στο χώρο επεναλήψεων με επακτάσιμο και σχεδόν βέλτιστο τρόπο. Στο δεύτερο τμήμα της διατριβής, μια DSE μεθοδολογία αναπτύχθηκε για το σχεδιασμό ενός προκαθορισμένου τομέα από εφαρμογές σε μια μερικώς αποφασισμένη αρχιτεκτονική πλατφόρμα, η οποία αποτελείται από ένα πυρήνα επεξεργαστή και αρκετούς συνεπεξεργαστές. Η DSE μεθοδολογία αποτελείται από μονής κατεύθυνσης βήματα, τα οποία υλοποιούνται μέσω παραμετρικών πλαισίων και εφαρμόζονται αποφέυγοντας τις δαπανηρές επαναλήψεις κατά τον σχεδιασμό. Η προτεινόμενη DSE μεθοδολογία εξερευνά το χώρο βρίσκοντας στιγμιότυπα για καθε βήμα και διαδίδονατς τις αποφάσεις μεταξύ βημάτων. Με αυτό το τρόπο κλαδεύουν τις επιλογές σχεδιασμού στα επόμενα βήματα. Το αποτέλεσμα είναι μια Pareto καμπύλη. Ένα DSE πλαίσιο προτάθηκε που περιγράφει τις τεχνικές χρονοπρογραμματισμού και ανάθεσης πόρων των καταχωρητών και των μονάδων εκτέλεσης του συστήματος. Προτάθηκε μια μεθοδολογία για να δημιουργεί σχεδόν βέλτιστα και επεκτάσιμα παραμετρικά πρότυπα για τον χρονοπρογραμματισμό και την ανάθεση πόρων που ικανοποιεί τους περιορισμούς ενός τομέα εφαρμογών.

The desire to enhance and make ourselves better is not a new one and it has continued to intrigue throughout the ages. Individuals have continued to seek ways to improve and enhance their well-being for example through nutrition, physical exercise, education and so on. Crucial to this improvement of their well-being is improving their ability to remember. Hence, people interested in improving their well-being, are often interested in memory as well. The rationale being that memory is crucial to our well-being. The desire to improve one’s memory then is almost certainly as old as the desire to improve one’s well-being. Traditionally, people have used different means in an attempt to enhance their memories: for example in learning through storytelling, studying, and apprenticeship. In remembering through practices like mnemonics, repetition, singing, and drumming. In retaining, storing and consolidating memories through nutrition and stimulants like coffee to help keep awake; and by external aids like notepads and computers. In forgetting through rituals and rites. Recent scientific advances in biotechnology, nanotechnology, molecular biology, neuroscience, and information technologies, present a wide variety of technologies to enhance many different aspects of human functioning. Thus, some commentators have identified human enhancement as central and one of the most fascinating subject in bioethics in the last two decades. Within, this period, most of the commentators have addressed the Ethical, Social, Legal and Policy (ESLP) issues in human enhancements as a whole as opposed to specific enhancements. However, this is problematic and recently various commentators have found this to be deficient and called for a contextualized case-by-case analysis to human enhancements for example genetic enhancement, moral enhancement, and in my case memory enhancement (ME). The rationale being that the reasons for accepting/rejecting a particular enhancement vary depending on the enhancement itself. Given this enormous variation, moral and legal generalizations about all enhancement processes and technologies are unwise and they should instead be evaluated individually. Taking this as a point of departure, this research will focus specifically on making a case for ME and in doing so assessing the ESLP implications arising from ME. My analysis will draw on the already existing literature for and against enhancement, especially in part two of this thesis; but it will be novel in providing a much more in-depth analysis of ME. From this perspective, I will contribute to the ME debate through two reviews that address the question how we enhance the memory, and through four original papers discussed in part three of this thesis, where I examine and evaluate critically specific ESLP issues that arise with the use of ME. In the conclusion, I will amalgamate all my contribution to the ME debate and suggest the future direction for the ME debate.