Global ETD Search

51	Time domain CMOS image sensor : from photodetection to on-chip image processing / Chen, Shoushun. January 2007 (has links) Thesis (Ph.D.)--Hong Kong University of Science and Technology, 2007. / Includes bibliographical references (leaves 135-145). Also available in electronic version.
52	Complementary orthogonal stacked metal oxide semiconductor a novel nanoscale complementary metal oxide semiconductor architecture / Al-Ahmadi, Ahmad Aziz. January 2006 (has links) Thesis (Ph.D.)--Ohio University, June, 2006. / Title from PDF t.p. Includes bibliographical references (p. [69]-[78])
53	Current-feedthrough cancellation techniques in switched-current circuits Lao, Paul A. 06 August 1990 (has links) Graduation date: 1991 Switched capacitor circuits
54	Fully-differential current-mode CMOS circuits and applications Zele, Rajesh H. 02 August 1990 (has links) With increasing interest in current-mode analogue processing due to its high performance properties such as speed, bandwidth and accuracy compared to voltage-mode processing, new current-mode alternatives to various conventional circuit designs are appearing. In this report, a novel circuit design to construct a fully-differential current-mode operational amplifier ( OP-AMP ) is suggested. A standard CMOS process and a 5 volt power supply are utilized. Simulation results using SPICE are presented. For the current-amplifier, a highly linear behavior ( THD 0.02% ) and an excellent frequency response ( 10 MHz ) were observed. Using this new differential OP-AMP topology, fully-differential switched-current delay cell and an integrator circuit were also developed successfully. / Graduation date: 1991 Electronic circuit design
55	Comparison and analysis of current-mode logic circuits with differential and static CMOS Shrivastava, Manu B. 07 February 1994 (has links) This thesis describes the analysis and comparison of Folded Source-Coupled Logic (FSCL) with standard static CMOS, cascode voltage-switch logic and differential split-level logic gates. The advantages of FSCL are low switching noise and high operating speed. The effect of voltage and device scaling on these topologies is evaluated in terms of average delay, power dissipation at maximum frequency, power-delay-product and current spike noise. Several two-summand adders are designed and simulated using MOSIS 1-μm CMOS process parameters and evaluations are performed in terms of area, delay, noise and power dissipation. / Graduation date: 1994
56	High frequency voltage controlled ring oscillators in standard CMOS Eken, Yalcin Alper 07 June 2004 (has links) No description available. Metal oxide semiconductors Complementary Oscillators Crystal
57	A substrate noise coupling model for lightly doped CMOS processes / Sadate, Aline C. January 1900 (has links) Thesis (M.S.)--Oregon State University, 2001. / Typescript (photocopy). Includes bibliographical references (leaves 33-35). Also available online.
58	Simulation and control of secondary electron programming in flash EEPROM's / Kencke, David Leighton, January 2000 (has links) Thesis (Ph. D.)--University of Texas at Austin, 2000. / Vita. Includes bibliographical references (leaves 97-112). Available also in a digital version from Dissertation Abstracts.
59	Single-ended 16x8 Gbps data bus in 90nm CMOS Mandhanya, Saurabh. January 2009 (has links) (PDF) Thesis (M.S. in electrical engineering)--Washington State University, December 2009. / Title from PDF title page (viewed on Jan. 21, 2010). "School of Electrical Engineering and Computer Science ." Includes bibliographical references (p. 73-75).
60	Optical receivers and photodetectors in 130nm CMOS technology Csutak, Sebastian Marius. January 2001 (has links) Thesis (Ph. D.)--University of Texas at Austin, 2001. / Vita. Includes bibliographical references. Available also from UMI/Dissertation Abstracts International.

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