The Jain and Balk analytic model for two-dimensional effects in short channel MOSFETS is investigated. The effects considered are Drain Induced Barrier Lowering, DIBL, and the maximum electric field, Emax, which influences Drain Induced High Field, DIHF. A scaled short channel design is used as the basis for the investigation. Cases are numerically simulated using the MINIMOS program. DIBL and Emax are calculated using the Jain and Balk model. Model values are compared to numerical simulation values. Results show the model consistently overestimates DIBL. Also, the range for which the model closely estimates Emax is found. Variation in Emax with change of junction depth Xj is investigated. The electric field, Ex, as it varies with depth in the channel is investigated, and compared to the Jain and Balk approximation. The deviations suggest that the model must break down for short channels.

A dissertation submitted to the Faculty of Science, Wits University, in fulfilment of the requirements for the degree of Master of Science. 30 March 2016. / Bismuth ferrite BiFeO3 is a transition metal oxide that exhibits both antiferromagnetic and ferroelectric orderings and is termed a magnetoelectric multiferroic. These functional properties make it crucial for applications in various nanoelectronic devices and sensors. However, the integration of BiFeO3 in devices requires the scaling down of bulk BiFeO3 to nano dimensional length scales in thin lm format. For this purpose, the elements of the elastic constant tensor of BiF eO3 thin lms are requisite, especially in multilayered or single layer-on-substrate device con gurations. It is thus essential that mechanical properties of BiFeO3 thin lms be established due to their size and growth mode dependence. Therefore, the study aims to determine the propagation of the surface acoustic waves and the elastic constants of BiFeO3 BFO thin lms in order to tailor the mechanical properties for device applications. In this approach the e ect of morphology and microstructure on the elastic constants has been investigated. / MT2016

Hiu Yung Wong. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2001. / Includes bibliographical references (leaves 104-111). / Abstracts in English and Chinese. / Abstract --- p.i / Acknowledgments --- p.iii / List of Figures --- p.ix / List of Tables --- p.xiii / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Motivation and Objectives --- p.1 / Chapter 1.2 --- Contributions --- p.3 / Chapter 1.3 --- Organization of the Thesis --- p.4 / Chapter 2 --- Devices and Fabrication Processes --- p.5 / Chapter 2.1 --- Introduction --- p.5 / Chapter 2.2 --- BJTs --- p.6 / Chapter 2.2.1 --- Structure and Modeling of BJTs --- p.6 / Chapter 2.2.2 --- Standard BJT Process and BJT Characteristics --- p.7 / Chapter 2.3 --- MOSFETs and Complementary MOS (CMOS) --- p.8 / Chapter 2.3.1 --- Structure and Modeling of MOSFETs --- p.8 / Chapter 2.3.2 --- Standard n-well CMOS Process and MOSFETs Charac- teristics --- p.11 / Chapter 2.4 --- BiCMOS Technology --- p.13 / Chapter 2.5 --- Summary --- p.14 / Chapter 3 --- Matching Properties --- p.15 / Chapter 3.1 --- Introduction --- p.15 / Chapter 3.2 --- Importance of Matched Devices in IC Design --- p.15 / Chapter 3.2.1 --- What is Matching? --- p.15 / Chapter 3.2.2 --- Low-power Systems --- p.16 / Chapter 3.2.3 --- Device Size Downward Scaling --- p.16 / Chapter 3.2.4 --- Analog Circuits and Analog Computing --- p.17 / Chapter 3.3 --- Measurement of Mismatch --- p.18 / Chapter 3.3.1 --- Definitions and Statistics of Mismatch --- p.18 / Chapter 3.3.2 --- Types of Mismatches --- p.20 / Chapter 3.3.3 --- Matching Properties of MOSFETs --- p.23 / Chapter 3.3.4 --- Matching Properties of BJTs and CLBTs --- p.27 / Chapter 3.4 --- Summary --- p.30 / Chapter 4 --- CMOS Compatible Lateral Bipolar Transistors (CLBTs) --- p.31 / Chapter 4.1 --- Introduction --- p.31 / Chapter 4.2 --- Structure and Operation --- p.32 / Chapter 4.3 --- DC Model of CLBTs --- p.34 / Chapter 4.4 --- Residual Gate Effect in Accumulation --- p.35 / Chapter 4.5 --- Main Characteristics of CLBTs --- p.37 / Chapter 4.5.1 --- Low Early Voltage --- p.37 / Chapter 4.5.2 --- Low Lateral Current Gain at High Current Levels --- p.38 / Chapter 4.5.3 --- Other Issues --- p.39 / Chapter 4.6 --- Enhanced CLBTs with Cascode Circuit --- p.40 / Chapter 4.7 --- Applications --- p.41 / Chapter 4.8 --- Design and Layout of CLBTs --- p.42 / Chapter 4.9 --- Experimental Results of Single pnp CLBT； nMOSFET and pMOSFET --- p.44 / Chapter 4.9.1 --- CLBT Gains --- p.46 / Chapter 4.9.2 --- Gate Voltage Required for Pure Bipolar Action --- p.47 / Chapter 4.9.3 --- I ´ؤ V and Other Characteristics of Bare pnp CLBTs --- p.49 / Chapter 4.9.4 --- Transfer Characteristics of a Cascoded pnp CLBT --- p.50 / Chapter 4.9.5 --- Transfer Characteristics of an nMOSFET --- p.51 / Chapter 4.9.6 --- Transfer Characteristics of Cascoded and Bare CLBTs Operating as pMOSFETs --- p.52 / Chapter 4.10 --- Summary --- p.53 / Chapter 5 --- Experiments on Matching Properties --- p.54 / Chapter 5.1 --- Introduction --- p.54 / Chapter 5.2 --- Objectives --- p.55 / Chapter 5.3 --- Technology --- p.57 / Chapter 5.4 --- Design of Testing Arrays --- p.57 / Chapter 5.4.1 --- nMOSFET Array --- p.57 / Chapter 5.4.2 --- pnp CLBT Array --- p.59 / Chapter 5.5 --- Design of Input and Output Pads (I/O Pads) --- p.62 / Chapter 5.6 --- Shift Register --- p.62 / Chapter 5.7 --- Experimental Equipment --- p.63 / Chapter 5.8 --- Experimental Setup for Matching Properties Measurements --- p.65 / Chapter 5.8.1 --- Setup for Measuring the Mismatches of the Devices --- p.65 / Chapter 5.8.2 --- Testing Procedures --- p.68 / Chapter 5.8.3 --- Data Analysis --- p.68 / Chapter 5.9 --- Matching Properties --- p.69 / Chapter 5.9.1 --- Matching Properties of nMOSFETs --- p.69 / Chapter 5.9.2 --- Matching Properties of CLBTs --- p.71 / Chapter 5.9.3 --- Matching Properties of pMOSFETs --- p.73 / Chapter 5.9.4 --- "Comments on the Matching Properties of CLBT, nMOSFET, and pMOSFET" --- p.76 / Chapter 5.9.5 --- "Mismatch in CLBT, nMOSFET, and pMOSFET Cur- rent Mirrors" --- p.77 / Chapter 5.10 --- Summary --- p.79 / Chapter 6 --- Conclusion --- p.80 / Chapter A --- Floating Gate Technology --- p.82 / Chapter A.1 --- Floating Gate --- p.82 / Chapter A.2 --- Tunnelling --- p.83 / Chapter A.3 --- Hot Electron Effect --- p.85 / Chapter A.4 --- Summary --- p.86 / Chapter B --- A Trimmable Transconductance Amplifier --- p.87 / Chapter B.1 --- Introduction --- p.87 / Chapter B.2 --- Trimmable Transconductance Amplifier using Floating Gate Com- patible Lateral Bipolar Transistors (FG-CLBTs) --- p.87 / Chapter B.2.1 --- Residual Gate Effect and Collector Current Modulation --- p.89 / Chapter B.2.2 --- Floating Gate CLBTs --- p.92 / Chapter B.2.3 --- Electron Tunnelling --- p.93 / Chapter B.2.4 --- Hot Electron Injection --- p.94 / Chapter B.2.5 --- Experimental Results of the OTA --- p.94 / Chapter B.2.6 --- Experimental Results of the FGOTA --- p.96 / Chapter B.3 --- Summary --- p.97 / Chapter C --- AMI-ABN 1.5μm n-well Process Parameters (First Batch) --- p.98 / Chapter D --- AMI-ABN 1.5μm n-well Process Parameters (Second Batch) --- p.101 / Bibliography --- p.104

by Fong Hon Hang = 超薄二氧化硅的固定電荷分佈和電擊穿特性 / 方漢鏗. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2000. / Includes bibliographical references. / Text in English; abstracts in English and Chinese. / by Fong Hon Hang = Chao bo er yang hua gui de gu ding dian he fen bu he dian ji chuan te xing / Fang Hankeng. / ABSTRACT --- p.i / ACKNOWLEDGEMENTS --- p.iii / TABLE OF CONTENT --- p.iv / LIST OF FIGURES --- p.ix / LIST OF TABLES --- p.xiv / LIST OF SYMBOLS --- p.xv / Chapter Chapter1 --- Background of the thesis work / Chapter 1.1 --- Introduction --- p.1 / Chapter 1.2 --- Stability of charge on oxide --- p.1 / Chapter 1.3 --- Defects in SiO2/Si --- p.2 / Chapter 1.4 --- Objectives of the thesis work --- p.4 / Chapter 1.5 --- Organization of the thesis --- p.5 / Bibliography for Chapter1 --- p.6 / Chapter Chapter2 --- Theory of X-ray Photoelectron Spectroscopy (XPS) and Surface Charge Spectroscopy (SCS) / Chapter 2.1 --- Introduction --- p.7 / Chapter 2.2 --- X-ray photoelectron spectrometry (XPS) --- p.8 / Chapter 2.2.1 --- Binding energy reference for semiconductors --- p.10 / Chapter 2.2.2 --- Measurement of surface Fermi level --- p.15 / Chapter 2.2.3 --- XPS quantitative analysis --- p.17 / Chapter 2.2.3.1 --- Electron Inelastic Mean free Path --- p.16 / Chapter 2.2.3.2 --- Atomic concentration of a homogeneous material --- p.17 / Chapter 2.2.3.3 --- Determination of overlayer thickness --- p.19 / Chapter 2.3 --- Surface charge Spectroscopy (SCS) --- p.21 / Chapter 2.3.1 --- Principle of the SCS technique --- p.21 / Chapter 2.3.2 --- Control of the dielectric surface potential --- p.21 / Chapter 2.3.3 --- Dielectric layer surface potential --- p.22 / Chapter 2.3.4 --- Surface band bending --- p.23 / Chapter 2.3.5 --- Limitation of the dielectric layer thickness --- p.24 / Chapter 2.4 --- Applications of SCS on Metal-Oxide Semiconductor (MOS) --- p.24 / Chapter 2.4.1 --- Measurements of interface state density (Dit) --- p.24 / Chapter 2.4.2 --- Determination of density of fixed-oxide charges --- p.27 / Bibliography for Chapter2 --- p.28 / Chapter Chapter3 --- Instrumentation & methodology / Chapter 3.1 --- X-ray Photoelectron Spectroscopy (XPS) --- p.30 / Chapter 3.1.1 --- General description of the Kratos AXIS - HS XPS system --- p.30 / Chapter 3.1.2 --- X-ray source --- p.32 / Chapter 3.1.3 --- AXIS - HS electron analyzer and transfer lens system --- p.35 / Chapter 3.1.4 --- Laser alignment facility --- p.38 / Chapter 3.1.5 --- In-lens (Micro XPS) aperture --- p.38 / Chapter 3.1.6 --- Iris (Lens input aperture) --- p.39 / Chapter 3.1.7 --- Magnetic immersion lenses --- p.39 / Chapter 3.1.8 --- Lateral resolutions --- p.41 / Chapter 3.1.9 --- Charge neutralizer --- p.53 / Chapter 3.1.10 --- XPS imaging capability --- p.58 / Chapter 3.1.11 --- Angle-resolved X-ray photoelectron spectroscopy (ARXPS) --- p.58 / Chapter 3.1.12 --- Ion sputtering system and depth profiling --- p.59 / Chapter 3.2 --- Methodology for surface charging --- p.59 / Chapter 3.3 --- Sample preparation --- p.61 / Bibliography for Chapter3 --- p.62 / Chapter Chapter4 --- Fixed-oxide charge Qf(z) of thermally-grown SiO2/Si(100) / Chapter 4.1 --- Introduction --- p.63 / Chapter 4.2 --- Experimental results on oxide surface potential as a function of oxide thickness --- p.64 / Chapter 4.3 --- Calculation of fixed-oxide charge distribution --- p.69 / Chapter 4.3.1 --- Gauss's law --- p.69 / Chapter 4.3.2 --- Density of fixed-oxide charge --- p.70 / Chapter 4.4 --- Applications --- p.78 / Bibliography for chapter4 --- p.80 / Chapter Chapter5 --- Observation of dielectric electrical breakdown phenomena of SiO2/Si structure by SCS / Chapter 5.1 --- Introduction to electrical breakdown analysis in device electronics --- p.81 / Chapter 5.2 --- Experimental --- p.82 / Chapter 5.3 --- Results --- p.82 / Chapter 5.3.1 --- Analysis on 1000A Sio2/Si --- p.82 / Chapter 5.3.1.1 --- Variation of C 1s under charging --- p.82 / Chapter 5.3.1.2 --- Stochastic breakdown of SiO2 --- p.84 / Chapter 5.3.2 --- Analysis on 19k SiO2/Si --- p.91 / Chapter 5.4 --- Discussion --- p.93 / Chapter 5.4.1 --- Model of stochastic breakdown of SiO2/Si --- p.93 / Chapter 5.4.2 --- Variation of Si 2p under charging --- p.95 / Chapter 5.5 --- Summary --- p.96 / Bibliography for Chapter5 --- p.99 / Chapter Chapter6 / Conclusion --- p.100

This dissertation explores the characteristics of Monotonic-Static CMOS and its potential applications in leakage reduction in ultra scaled Bulk-Si technology with significant gate leakage currents. Using test circuits consisting of different configurations of 16-bit lookahead adders, we performed a comparison among static, monotonic static and domino logic in terms of various properties including power, delay, noise margin and area. Comparisons were done over a wide range of possible transistor widths to fully characterize the tradeoffs for each circuit type. Experimental results show that MS-CMOS has potential advantages in some situations in terms of stand-by power, evaluation speed and noise margin in such a technology.

Thesis (Ph. D.)--University of Texas at Austin, 2006. / Vita. Includes bibliographical references.

Full integration of CMOS low noise amplifiers (LNA) presents a challenge for low cost CMOS receiver systems. A critical problem faced in the design of an RF CMOS LNA is the inaccurate high-frequency noise model of the MOSFET implemented in circuit simulators such as SPICE. Silicon-based monolithic inductors are another bottleneck in RF CMOS design due to their poor quality factor. In this thesis, a CMOS implementation of a fully-integrated differential LNA is presented. A small-signal noise circuit model that includes the two most important noise sources of the MOSFET at radio frequencies, channel thermal noise and induced gate current noise, is developed for CMOS LNA analysis and simulation. Various CMOS LNA architectures are investigated. The optimization techniques and design guidelines and procedures for an LC tuned CMOS LNA are also described. Analysis and modeling of silicon-based monolithic inductors and transformers are presented and it is shown that in fully-differential applications, a monolithic transformer occupies less die area and achieves a higher quality factor compared to two independent inductors with the same total effective inductance. It is also shown that monolithic transformers improve the common-mode rejection of the differential circuits. / Graduation date: 1999

High-accuracy and high-speed CMOS track-and-hold (T/H) or sample-and-hold (S/H) circuits are an important part of the analog-to-digital interface. The switched-capacitor (SC) circuits usually contain one or more op-amps whose dc offset, finite gain, finite bandwidth have a big impact on the accuracy of the track-and-hold circuit. Basic correlated double sampling (CDS) scheme can reduce such effects, but the compensation that it provides may not be good enough for high-accuracy application. Also, the high-quality analog poly-poly capacitors used in most SC circuits are not available in a basic digital CMOS process. The MOSFET-only predictive track-and-hold circuit, discussed in this thesis, replaces the poly-poly capacitors with easily-available low-cost area-saving MOSFET capacitors biased in accumulation region. It also uses the predictive correlated double sampling (CDS) scheme, in which the op-amp predicts its output for the next clock period during the present clock period, so that the adjacent two output samples are nearly the same. The predictive operation results in more correlation between the unwanted signal and the signal that is subtracted during the double sampling, and hence can achieve offset and gain compensation over wider frequency range. Hence, this circuit is suitable for high-accuracy applications, while using only a basic digital process. / Graduation date: 1997

Thesis (Ph. D.)--University of Texas at Austin, 2006. / Vita. Includes bibliographical references.

Thesis (Ph. D.)--University of Florida, 2005. / Title from title page of source document. Document formatted into pages; contains 157 pages. Includes vita. Includes bibliographical references.