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  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
31

Hot-carrier reliability simulation in aggresively scaled MOS transistors

Pagey, Manish Prabhakar. January 2003 (has links)
Thesis (Ph. D. in Electrical Engineering)--Vanderbilt University, 2003. / Title from PDF title screen. Includes bibliographical references.
32

Enhanced defect generation in gate oxides of P-channel MOS transistors in the presence of water

Dasgupta, Aritra. January 2009 (has links)
Thesis (M. S. in Electrical Engineering)--Vanderbilt University, May 2009. / Title from title screen. Includes bibliographical references.
33

Source/drain engineering for extremely scaled MOSFETs /

Zhang, Zhikuan. January 2005 (has links)
Thesis (Ph.D.)--Hong Kong University of Science and Technology, 2005. / Includes bibliographical references. Also available in electronic version.
34

Compact modeling of double-gate metal-oxide-semiconductor field-effect transistor /

Shi, Xuejie. January 2006 (has links)
Thesis (Ph.D.)--Hong Kong University of Science and Technology, 2006. / Includes bibliographical references. Also available in electronic version.
35

Heteroepitaxial Ge on Si via High-Bandgap III-V Buffers for Low-Power Electronic Applications

Nguyen, Peter D. 23 June 2016 (has links)
Over the past four decades, aggressive scaling of silicon (Si) based complementary metal-oxide-semiconductor (CMOS) transistors has resulted in an exponential increase in device density, and thus an exponential increase in computing power. Increasing transistor density also results in increasing total power consumption and thus, necessitates supply voltage scaling in order to maintain low-power device operation. However, with increased supply voltage scaling, transistor drive current is significantly degraded due to the low carrier mobility of Si. To overcome the key challenges of device and voltage scaling required for low-power electronic operation without the degradation of transistor drive current requires the adoption of narrow bandgap channel materials with superior transport properties. However, the use of such materials as bulk substrates remains cost-prohibitive. Thus, another key challenge lies in the heterogeneous integration of high-mobility channel materials on affordable, established Si platform. Germanium (Ge) is an attractive candidate for next-generation low-power devices owing to its high electron and high hole mobility. Recently, AlAs/GaAs epilayers were demonstrated as a potential buffer platform for next-generation Ge-based electronics integrated on Si substrate. This research systematically investigates the structural characteristics of the Ge epitaxial layer heterogeneously integrated on Si using a composite III-V AlAs/GaAs buffer and the electrical characteristics of MOS capacitors (MOS-C's) fabricated on the aforementioned stack. Further passivation techniques and interface engineering is then pursued on MOS-C's fabricated from (100) and (110) crystallographically oriented epitaxial Ge integrated on AlAs/GaAs material stacks, balancing out effective oxide thickness (EOT) and reduction of oxide and interfacial traps in order to ensure a pristine interfacial quality for high-performance electronic applications. Further, work function tuning is demonstrated for the first time on the different crystallographically oriented epitaxial Ge integrated on AlAs/GaAs material stacks using two different gate metals, demonstrating the tunability of threshold voltage, VTH, required for transistor applications. The research demonstrates the feasibility of future high-mobility channel material integration on Si via large bandgap buffer architectures for high-speed, low-power, high-performance CMOS logic applications. / Master of Science
36

Characterization of interface trap density in power MOSFETs using noise measurements

Huang, Chender, 1960- January 1988 (has links)
Low-frequency noise has been measured on commercial power MOSFETs. These devices, fabricated with the VDMOS structure, exhibit a 1/f type noise spectrum. The interface state density obtained from noise measurements was compared with that obtained from the subthreshold-slope method. Reasonable agreement was found between the two measurements. The radiation effects on the noise power spectral density were also investigated. The results indicated that the noise can be attributed to the generation of interface traps near the Si-SiO₂ interface. The level of interface traps generated by radiation was bias dependent. The positive gate bias gave rise to the largest interface-trap density.
37

A study of surface-related low-frequency noise in MOSFETs and metal films

王曦, Wong, Hei. January 1990 (has links)
published_or_final_version / Electrical and Electronic Engineering / Doctoral / Doctor of Philosophy
38

The analysis of current-mirror MOSFETs for use in radiation environments

Martinez, Marino Juan, 1965- January 1988 (has links)
Experiments were conducted on current-mirror MOSFETs to examine their suitability for use in radiation environments. These devices, which allow low loss load current sensing (defined by a current-ratio n'), are an important element of many power integrated circuits (PICs). Total-dose testing demonstrated that the current ratio was virtually unaffected for many operating conditions. In all cases, changes were largest when sense resistance was largest and minimal when sense voltage was approximately equal to the load source's voltage. In addition, testing verified the feasibility of using sense-cell MOSFETs for applications which require radiation exposure. A constant-current op-amp circuit showed minimal current shifts, using proper circuit design, following total-dose exposure. Dose-rate testing showed the feasibility of using sense voltage to trigger g&d2; protection through drain-source voltage clamping, providing a relatively inexpensive alternative to voltage derating.
39

Fast-neutron-induced resistivity change in power MOSFETs

Safarjameh, Kourosh, 1961- January 1989 (has links)
Fast neutron irradiation tests were performed to determine the correlation of change of drain-source resistance and neutron fluence for power MOSFETs. The Objectives of the tests were: (1) to detect and measure the degradation of critical MOSFET device parameters as a function of neutron fluence (2) to compare the experimental results and the theoretical model. In general, the drain-source resistance increased from 1 Ohm to 100 Ohm after exposure to fast neutron fluence of 3 x 1014 neut/cm2, and decreased by a factor of five after high temperature annealing.
40

Simulation of radiation-induced parametric degradation in electronic amplifiers

Barbara, Nabil Victor, 1964- January 1989 (has links)
Many high performance amplifiers use power MOSFETs in their output stages, especially in operational amplifier applications whenever high current or power is needed. MOSFETs have advantages over bipolar transistors in amplifier output stage because MOSFETs are majority carrier devices. The result is wide frequency response, fast switching and better linearity than power bipolar transistors. But unlike bipolar circuits, which are relatively tolerant of ionizing radiation, MOSFETs may suffer severe parametric degradation at low total-dose levels. The effects of ionizing radiation on MOSFETs are discussed, and the performance of an amplifier circuit that uses a complementary MOSFET source follower in its output stage is simulated to examine the effect of MOSFET radiation damage on amplifier performance. An increase in power dissipation was the most significant degradation caused by ionizing radiation.

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