A inclusão de fontes alternativas no sistema de energia elétrica possibilita a otimização dos recursos naturais disponíveis para geração. A conexão dessas fontes deve ser efetuada de forma a evitar índices de qualidade de energia incondizentes aos limites estabelecidos por normas nacionais e internacionais. Nesse contexto, sistemas de Geração Distribuída (GD) conectados à rede de distribuição via controle tensão/potência utilizam controladores Proporcional+Ressonantes (P+R) para produzir tensões com mínimas distorções na presença de cargas não lineares. Além disso, esse tipo de solução apresenta resultados satisfatórios na presença de outros tipos de carga (linear, não linear e conexão de máquina de indução), entretanto, para uma carga RLC com frequência de ressonância igual à frequência fundamental, o sistema de GD torna-se instável e as distorções harmônicas ultrapassam os limites mínimos estabelecidos para assegurar a qualidade de energia. Dessa forma, essa dissertação de mestrado propõe a substituição do controlador P+R da frequência fundamental por um controlador de ordem fracionária PIλ, projetado através de um algoritmo de otimização heurística. Os resultados obtidos através de simulação demonstram que o controlador proposto apresenta resultados satisfatórios para todas as cargas testadas: Não Linear; Motor de Indução Trifásico e RLC com frequência de ressonância igual à fundamental da rede. Entretanto, os resultados experimentais mostraram uma sensibilidade quanto à mudança de carga e quanto aos parâmetros de discretização do controlador, sugerindo a necessidade de uma análise mais rigorosa na etapa de projeto de modo a se ter robustez quanto à variação de carga. / The insertion of alternative sources in the power system enables the optimization of natural resources available for electrical generation. The connection of these sources to the grid has to be made in order to avoid indices of power quality greater than the limits established by national and international standards. In this context, a Distributed Generation (DG) systems connected to the grid via voltage/power control use a proportional+resonant (P+R) controller to produce not only the fundamental frequency but also to reduce the voltage distortion when nonlinear loads are connected to the DG terminals. Additionally, this type of solution shows satisfactory results for linear, balanced, unbalanced and direct connection of induction machine as well. However, for parallel RLC load with frequency of resonance equals to the fundamental frequency of the grid, the DG system operation becomes unstable with high levels of harmonic distortions and an oscillatory behavior. In this context, we propose the replacement of the PR controller for the fundamental frequency by a fractional order controller PIλ designed via a heuristic optimization algorithm. To prove the feasibility of the proposed approach a set of simulations are presented, however, the experimental prototype shown the sensitivity of the controller for different loads and for the controller discretization parameters suggesting the need for more analysis during the design procedures of the PIλ controller to achieve the expected robustness.

A inclusão de fontes alternativas no sistema de energia elétrica possibilita a otimização dos recursos naturais disponíveis para geração. A conexão dessas fontes deve ser efetuada de forma a evitar índices de qualidade de energia incondizentes aos limites estabelecidos por normas nacionais e internacionais. Nesse contexto, sistemas de Geração Distribuída (GD) conectados à rede de distribuição via controle tensão/potência utilizam controladores Proporcional+Ressonantes (P+R) para produzir tensões com mínimas distorções na presença de cargas não lineares. Além disso, esse tipo de solução apresenta resultados satisfatórios na presença de outros tipos de carga (linear, não linear e conexão de máquina de indução), entretanto, para uma carga RLC com frequência de ressonância igual à frequência fundamental, o sistema de GD torna-se instável e as distorções harmônicas ultrapassam os limites mínimos estabelecidos para assegurar a qualidade de energia. Dessa forma, essa dissertação de mestrado propõe a substituição do controlador P+R da frequência fundamental por um controlador de ordem fracionária PIλ, projetado através de um algoritmo de otimização heurística. Os resultados obtidos através de simulação demonstram que o controlador proposto apresenta resultados satisfatórios para todas as cargas testadas: Não Linear; Motor de Indução Trifásico e RLC com frequência de ressonância igual à fundamental da rede. Entretanto, os resultados experimentais mostraram uma sensibilidade quanto à mudança de carga e quanto aos parâmetros de discretização do controlador, sugerindo a necessidade de uma análise mais rigorosa na etapa de projeto de modo a se ter robustez quanto à variação de carga. / The insertion of alternative sources in the power system enables the optimization of natural resources available for electrical generation. The connection of these sources to the grid has to be made in order to avoid indices of power quality greater than the limits established by national and international standards. In this context, a Distributed Generation (DG) systems connected to the grid via voltage/power control use a proportional+resonant (P+R) controller to produce not only the fundamental frequency but also to reduce the voltage distortion when nonlinear loads are connected to the DG terminals. Additionally, this type of solution shows satisfactory results for linear, balanced, unbalanced and direct connection of induction machine as well. However, for parallel RLC load with frequency of resonance equals to the fundamental frequency of the grid, the DG system operation becomes unstable with high levels of harmonic distortions and an oscillatory behavior. In this context, we propose the replacement of the PR controller for the fundamental frequency by a fractional order controller PIλ designed via a heuristic optimization algorithm. To prove the feasibility of the proposed approach a set of simulations are presented, however, the experimental prototype shown the sensitivity of the controller for different loads and for the controller discretization parameters suggesting the need for more analysis during the design procedures of the PIλ controller to achieve the expected robustness.

<p>During the past years has the Nostrum Network on Chip <i>(NoC)</i> been developed to become a competitive platform for network based on-chip communication. The Nostrum NoC provides a versatile communication platform to connect a large number of intellectual properties <i>(IP) </i>on a single chip. The communication is based on a packet switched network which aims for a small physical footprint while still providing a low communication overhead. To reduce the communication network size, a queue-less network has been the research focus. This network uses de ective hot-potato routing which is implemented to perform routing decisions in a single clock cycle.</p><p>Using a platform like this results in increased design reusability, validated signal integrity, and well developed test strategies, in contrast to a fully customised designs which can have a more optimal communication structure but has a significantly longer development cycle to verify the new design accordingly.</p><p>Several factors are considered when designing a communication platform. The goal is to create a platform which provides low communication latency, high throughput, low power consumption, small footprint, and low design, verification, and test overhead. Proximity Congestion Awareness is one technique that serves to reduce</p><p>the network load. This leads to that the latency is reduced which also increases the network throughput. Another technique is to implement low latency paths called<i> Data Motorways</i> achieved through a clocking method called Globally Pseudochronous Locally Synchronous clocking. Furthermore, virtual circuits can be used to provide guarantees on latency and throughput. Such guarantees are dificult in</p><p>hot-potato networks since network access has to be ensured. A technique that implements virtual circuits use looped containers that are circulating on a predefined circuit. Several overlapping virtual circuits are possible by allocating the virtual circuits in different Temporally Disjoint Networks.</p><p>This thesis summarise the impact the presented techniques and methods have on the characteristics on the Nostrum model. It is possible to reduce the network load by a factor of 20 which reduces the communication latency. This is done by distributing load information between the Switches in the network. Data Motorways</p><p>can reduce the communication latency with up to 50% in heavily loaded networks. Such latency reduction results in freed buffer space in the Switch registers which allows the traffic rate to be increased with about 30%.</p>

During the past years has the Nostrum Network on Chip (NoC) been developed to become a competitive platform for network based on-chip communication. The Nostrum NoC provides a versatile communication platform to connect a large number of intellectual properties (IP) on a single chip. The communication is based on a packet switched network which aims for a small physical footprint while still providing a low communication overhead. To reduce the communication network size, a queue-less network has been the research focus. This network uses de ective hot-potato routing which is implemented to perform routing decisions in a single clock cycle. Using a platform like this results in increased design reusability, validated signal integrity, and well developed test strategies, in contrast to a fully customised designs which can have a more optimal communication structure but has a significantly longer development cycle to verify the new design accordingly. Several factors are considered when designing a communication platform. The goal is to create a platform which provides low communication latency, high throughput, low power consumption, small footprint, and low design, verification, and test overhead. Proximity Congestion Awareness is one technique that serves to reduce the network load. This leads to that the latency is reduced which also increases the network throughput. Another technique is to implement low latency paths called Data Motorways achieved through a clocking method called Globally Pseudochronous Locally Synchronous clocking. Furthermore, virtual circuits can be used to provide guarantees on latency and throughput. Such guarantees are dificult in hot-potato networks since network access has to be ensured. A technique that implements virtual circuits use looped containers that are circulating on a predefined circuit. Several overlapping virtual circuits are possible by allocating the virtual circuits in different Temporally Disjoint Networks. This thesis summarise the impact the presented techniques and methods have on the characteristics on the Nostrum model. It is possible to reduce the network load by a factor of 20 which reduces the communication latency. This is done by distributing load information between the Switches in the network. Data Motorways can reduce the communication latency with up to 50% in heavily loaded networks. Such latency reduction results in freed buffer space in the Switch registers which allows the traffic rate to be increased with about 30%. / QC 20101122