O Trabalho de dissertação se baseia principalmente nos livros Sobre a Potencialidade da Alma: De quantitate animae e De libero arbítrio, escritos por Santo Agostinho. Discorremos sobre o processo de conceituação do ente alma e da solução do problema do livre arbítrio através do sistema pedagógico agostiniano circuitum nostrum. Veremos que esse ente imaterial que nos faz racionais e, portanto, humanos, é o que mais se aproxima de Deus, de todos os entes da criação. Um ente Imortal, com ideias inatas, sem divisão e que monitora todas as funções do corpo, possibilitando ao ser humano o uso das memórias, da razão e da racionalidade. Subsistindo em si mesma, ela permanece mesmo depois da separação do corpo, como uma entidade única e portadora de todas as lembranças do corpo que animava para a vida. Apresentando-se como um dualista, Santo Agostinho, nos revela que embora a alma esteja no corpo ela não está presa ao corpo, porém no corpo. Sem crescimento ou envelhecimento esse ente imaterial, sem dimensões é real, porém desconhecido do próprio sujeito que a acolhe. Um ente que mantém o princípio vital e de animação (animus) do corpo. Quando essa alma é educada pela racionalidade permite ao ser humano o uso pleno da liberdade na escolha moral do agir, ou livre arbítrio. Veremos que a influência de Sócrates, Platão e do neoplatonismo através dos diálogos inseridos no sistema pedagógico agostiniano circuitum nostrum e, a relação entre o pedagogismo de Paulo Freire como um espelho do agostiniano, através do diálogo como produtores de sujeitos ativos na transformação da sociedade. / This thesis is based mainly on the books About the Potentiality of the Soul: De quantitate animae and De libero arbítrio written by Saint Augustine. We discourse about the process of conceptualization of the being soul and of the solution of the problem of free choice through the Augustinian pedagogical system circuitum nostrum. We will see that this immaterial being which makes us rational, and therefore human, is what comes closest to God of all the beings of the creation. An immortal being, with innate ideas, without division and which monitors all the functions of the body, making it possible for the human being to use the memory, reason and rationality. Subsisting in itself, it remains, even after the separation from the body, as a whole entity and carrier of all the memories of the body which animated it for life. Presenting himself as a dualist, St. Augustine reveals to us that although the soul is in the body it is not bound to the body, but is in the body. Without growth and aging this immaterial being without dimensions is real, however unknown to the subject him/her self who houses it. A being which maintains the vital principle and that of animation (animus) of the body. When this soul is educated by rationality it permits the human being the full use of freedom in the moral choice of action, or free will. We will see the influence of Socrates, Plato and neoplatonism through the dialogs inserted in the Augustinian pedagogical system circuitum nostrum and the relation between the pedagogism of Paulo Freire as a mirror of augustinianism, through the dialog as producers of active subjects in the transformation of society.

Moore’s law is the observation that over the years, the transistor density will increase,allowing billions of transistors to be integrated on a single chip. Over the lasttwo decades, Moore’s law has enabled the implementation of complex systems on asingle chip(SoCs). The challenge of the System-on-Chip(SoC) era was the demandof an efficient communication mechanism between the growing number of processingcores on the chip. The outcome established an new interconnection scheme (amongothers, like crossbars, rings, buses) based on the telecommunication networks andthe Network- on-Chip(NoC) appeared on the scene.The NoC has been developed not only to support systems embedded into asingle processor, but also to support a set of processors embedded on a singlechip.Therefore, the Multi-Processors System on Chip(MPSoC) has arisen, whichincorporate processing elements, memories and I/O with a fixed interconnection infrastructurein a complete integrated system. In such systems, the NoC constitutesthe backbone of the communication architecture that targets future SoC composedby hundred of processing elements. Besides that, together with the deep sub-microntechnology progress, some drawbacks have arisen. The communication efficiencyand the reliability of the systems rely on the proper functionality of NoC for onchipdata communication. A NoC must deal with the susceptibility of transistors tofailure that indicates the demand for a fault tolerant communication infrastructure.A mechanism that can deal with the existence of different classes of faults(transient,intermittent and permanent [11]) which can occur in the communication network.In this thesis, different algorithms are investigated that implement fault toleranttechniques for permanent faults in the NoC. The outcome would be to deliver a faulttolerantmechanism for the NoC System Generator Tool [29] which is a researchin Network-on-Chip carried out at the Royal Institute of Technology. It will beexplicitly described the fault tolerant algorithm that is implemented in the switchin order to achieve packet rerouting around the faulty communication links.

<p>During the past years has the Nostrum Network on Chip <i>(NoC)</i> been developed to become a competitive platform for network based on-chip communication. The Nostrum NoC provides a versatile communication platform to connect a large number of intellectual properties <i>(IP) </i>on a single chip. The communication is based on a packet switched network which aims for a small physical footprint while still providing a low communication overhead. To reduce the communication network size, a queue-less network has been the research focus. This network uses de ective hot-potato routing which is implemented to perform routing decisions in a single clock cycle.</p><p>Using a platform like this results in increased design reusability, validated signal integrity, and well developed test strategies, in contrast to a fully customised designs which can have a more optimal communication structure but has a significantly longer development cycle to verify the new design accordingly.</p><p>Several factors are considered when designing a communication platform. The goal is to create a platform which provides low communication latency, high throughput, low power consumption, small footprint, and low design, verification, and test overhead. Proximity Congestion Awareness is one technique that serves to reduce</p><p>the network load. This leads to that the latency is reduced which also increases the network throughput. Another technique is to implement low latency paths called<i> Data Motorways</i> achieved through a clocking method called Globally Pseudochronous Locally Synchronous clocking. Furthermore, virtual circuits can be used to provide guarantees on latency and throughput. Such guarantees are dificult in</p><p>hot-potato networks since network access has to be ensured. A technique that implements virtual circuits use looped containers that are circulating on a predefined circuit. Several overlapping virtual circuits are possible by allocating the virtual circuits in different Temporally Disjoint Networks.</p><p>This thesis summarise the impact the presented techniques and methods have on the characteristics on the Nostrum model. It is possible to reduce the network load by a factor of 20 which reduces the communication latency. This is done by distributing load information between the Switches in the network. Data Motorways</p><p>can reduce the communication latency with up to 50% in heavily loaded networks. Such latency reduction results in freed buffer space in the Switch registers which allows the traffic rate to be increased with about 30%.</p>

Abstract not available.

During the past years has the Nostrum Network on Chip (NoC) been developed to become a competitive platform for network based on-chip communication. The Nostrum NoC provides a versatile communication platform to connect a large number of intellectual properties (IP) on a single chip. The communication is based on a packet switched network which aims for a small physical footprint while still providing a low communication overhead. To reduce the communication network size, a queue-less network has been the research focus. This network uses de ective hot-potato routing which is implemented to perform routing decisions in a single clock cycle. Using a platform like this results in increased design reusability, validated signal integrity, and well developed test strategies, in contrast to a fully customised designs which can have a more optimal communication structure but has a significantly longer development cycle to verify the new design accordingly. Several factors are considered when designing a communication platform. The goal is to create a platform which provides low communication latency, high throughput, low power consumption, small footprint, and low design, verification, and test overhead. Proximity Congestion Awareness is one technique that serves to reduce the network load. This leads to that the latency is reduced which also increases the network throughput. Another technique is to implement low latency paths called Data Motorways achieved through a clocking method called Globally Pseudochronous Locally Synchronous clocking. Furthermore, virtual circuits can be used to provide guarantees on latency and throughput. Such guarantees are dificult in hot-potato networks since network access has to be ensured. A technique that implements virtual circuits use looped containers that are circulating on a predefined circuit. Several overlapping virtual circuits are possible by allocating the virtual circuits in different Temporally Disjoint Networks. This thesis summarise the impact the presented techniques and methods have on the characteristics on the Nostrum model. It is possible to reduce the network load by a factor of 20 which reduces the communication latency. This is done by distributing load information between the Switches in the network. Data Motorways can reduce the communication latency with up to 50% in heavily loaded networks. Such latency reduction results in freed buffer space in the Switch registers which allows the traffic rate to be increased with about 30%. / QC 20101122