Optical communication is distinguished for its enormous interconnect capacity over long distance. As the cost of optical components drops, high bandwidth optical systems were successfully employed into local area network and computer racks because electrical counterparts are not able to deal with the data rate demands for these applications. With the popularity of multi-core CPU in High Performance Computers, the board-to-board interconnects exclusive based on electrical technology in backplane applications become insufficient because of not only bandwidth crises, but also wiring congestions. Many researches have projected that the progress of optical technology will further push down the boundary demarcating electrical and optical domains in the interconnect hierarchy. Accordingly, backplane or even board-to-board level interconnects will benefit from the complement of optical interconnect. From architecture point of view, an optical bus implementation of the optical interconnect has the potential advantage of both huge bandwidth and elimination of wiring congestion. In contrast, optical waveguide and free-space interconnects although provide high bandwidth capacity, are essentially point-to-point technology which requires routing to a central switch on the backplane. The centralized approach that was based on substrate guided optical interconnects is the only way known that fulfills a uniform fan-out for different nodes in a bus architecture, which allows medium sharing among nodes. In this dissertation, innovative bit-interleaved optical backplane bus architecture is created based on centralized substrate-guide optical interconnect, which allows the tremendous bandwidth capacity to be shared by retaining the share bus architecture. Therefore, a secure and reliable high speed transmission channel could be established by distributing copies of confidential information separately. The feature provided by this innovative design cannot be fulfilled using electrical interconnects or other optical point-to-point technology without causing wiring congestions. In this dissertation, the optical characteristics of the centralized optical bus such as bandwidth and alignment tolerance are analyzed so that multi-channel implementation are successful on the fabricated optical interconnect layer. A 3-board-16-channel computer server using optical backplane board demonstrator using centralized optical bus was built upon the simulation, design and packaging work.

Even with the performance of microprocessors expected to double within the next three to five years, the processing power increase offered by parallel processing has made multiprocessor systems very cost-effective. Each module in the multiprocessor systems will typically include a processor, coprocessor, cache, and main memory. This kind of architecture has generated the system-on-aboard distributed-intelligence concept, and the 32-bit multimaster buses thus come into play since these high-performance systems need to communicate with each other. During communication, commands and large blocks of data are transmitted across the bus. Along with the multiprocessor system, the single-CPU system continues to need a fast bus and wide data path to serve as a common I/O interface for terminals, disk storage devices, communication, and memory boards. With the board size limited, the trend toward distributed intelligence increases the need to place more functions on a single board, and therefore bus interface unit (BIU) integrated circuits (ICs) play an important role in the design of new boards. Spaceborn systems must be fault-tolerant due to their high susceptibility to transient faults and the high costs of repair and maintenance. Hence, a gate array fault-tolerant bus-interface IC based on modified NuBus protocols is designed to meet these requirements. The gate array IC design system HIGHLAND from United Technologies Microelectronics Center is used, along with other CAD tools such as the Berkeley VLSI Tool Set and LOGEN to generate a layout for the BIU. Two programs are written to interface the necessary CAD tools. All the circuits are designed and simulated on a VAXstation 3200 (Ultrix-32) and VAX11/785 (VMS). / Master of Science

Integrated Circuit (IC) designs are increasingly moving towards Intellectual Property (IP) reuse for various targeted products and market segments. Therefore, there is a need to share and synergize internal bus architectures to enable the reuse of IP blocks for various ASIC and SoC applications. Due to the different market segments of various ASICs and SoCs, design teams and architects have opted to use customized internal bus architectures to suit the respective targeted features for their market segments. As a result, many ASIC and SoC companies that produce microprocessors for computers, microcontrollers for consumer electronics as well as memory and I/O controller chipsets have opted to use different internal interfaces, designs and IPs for the different products that they sell. A modular and configurable bus architecture that is flexible and capable of supporting IPs from various ASICs and SoCs would serve to solve many of the problems relating to IP reuse for various applications from a front end design perspective. There are several approaches to resolve this, for example, using a standard existing open source bus, a new all-encompassing bus that covers the needs of the majority of designs and a customization of a particular bus level such as the interface layer, where part of the bus features are fixed and the rest of them are determined by individual design groups. This research covers the analysis of existing bus architectures in industry and considers the various options for bus architecture optimization for design modularity, bus performance and IP reuse with existing technology. The architecture definition, design, logic simulation and performance comparisons of the proposed bus architecture on industry standard RTL design and validation tools was then conducted.

This paper describes the building of a parallel converter for a high-speed serial bus. The high-speed serial port of the Macintosh personal computer is used to implement the bus, while an MC68000 Educational Computer Board is used to perform the serial-to-parallel conversion. The device's performance is evaluated, and possible methods for improving its performance are discussed.

The advent of the Personal Computer into the technical world has, at an extremely reasonable expense and trouble, made available to us, considerable computational power. But, as it was with computers, the next logical step is to have multiple units running in concert, or, in other words, sharing the load. This leads to the concept of Multiprocessing in order to attain an enhancement in operation speed and superior efficiency. The IBM PC is a versatile and market proven personal computer with a very large volume of software support and the STD Bus is a standard that has been developed to cope with a variable support, i.e. different processors and different I/O capabilities. Together, they combine the user interface - the display and keyboard · of the PC, the processing capabilities of the PC, the I/O capabilities of the STD Bus and the support processing possible on the STD Bus. The resulting system is powerful, easy to use and it has a lot of scope for development. / Master of Science

Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1980. / MICROFICHE COPY AVAILABLE IN ARCHIVES AND ENGINEERING. / Includes bibliographcial references. / by Helen Louise Graham. / M.S.