As the world moves towards eliminating lead from consumer products, the microelectronics industry has put effort into developing lead-free solder paste. The major drawback of lead-free solder is the problems caused by its high reflow temperature. Variable frequency microwave (VFM) processing has been shown to allow some materials to be processed at lower temperatures. Issues addressed in this study include using VFM to reduce the solder reflow temperature, comparing the heating rate of different size solder particles, and comparing the reliability of VFM reflowed solder versus conventionally reflowed solder. Results comparing the effect of particle size on the heating rate of solder showed that the differences were negligible. This is due in part to the particle sizes overlapping. Many lead-free solder pastes reflow around 250℃. Results indicate that when using the VFM, lead-free solder paste will reflow at 220℃. The reliability of solder that was reflowed using the VFM at the reduced temperature was found to be comparable to solder reflowed in a conventional manner. Based on these findings, VFM processing can eliminate the major obstacles to making lead-free solder paste a more attractive option for use in the microelectronics industry.

Microelectronics has enjoyed great success in the past century. As the technology node progresses, the complementary metal-oxide-semiconductor scaling has already reached a wall, and serious challenges in high-bandwidth interconnects and fast-speed signal processing arise. The incorporation of photonics to microelectronics provides potential solutions. The theme of this thesis is focused on the novel applications of travelling-wave microresonators such as microdisks and microrings for the on-chip optical interconnects and signal processing. Challenges arising from these applications including theoretical and experimental ones are addressed. On the theoretical aspect, a modified version of coupled mode theory is offered for the TM-polarization in high index contrast material systems. Through numerical comparisons, it is shown that our modified coupled mode theory is more accurate than all the existing ones. The coupling-induced phase responses are also studied, which is of critical importance to coupled-resonator structures. Different coupling structures are studied by a customized numerical code, revealing that the phase response of symmetric couplers with the symmetry about the wave propagating direction can be simply estimated while the one of asymmetric couplers is more complicated. Mode splitting and scattering loss, which are two important features commonly observed in the spectrum of high-Q microresonators, are also investigated. Our review of the existing analytical approaches shows that they have only achieved partial success. Especially, different models have been proposed for several distinct regimes and cannot be reconciled. In this thesis, a unified approach is developed for the general case to achieve a complete understanding of these two effects. On the experimental aspect, we first develop a new fabrication recipe with a focus on the accurate dimensional control and low-loss performance. HSQ is employed as the electron-beam resist, and the lithography and plasma etching steps are both optimized to achieve vertical and smooth sidewalls. A third-order temperature-insensitive coupled-resonator filter is designed and demonstrated in the silicon-on-insulator (SOI) platform, which serves as a critical building block element in terabit/s on-chip networks. Two design challenges, i.e., a broadband flat-band response and a temperature-insensitive design, are coherently addressed by employing the redundant bandwidth of the filter channel caused by the dispersion as thermal guard band. As a result, the filter can accommodate 21 WDM channels with a data rate up to 100 gigabit/s per wavelength channel, while providing a sufficient thermal guard band to tolerate more than ±15°C temperature fluctuations in the on-chip environment. In this thesis, high-Q microdisk resonators are also proposed to be used as low-loss delay lines for narrowband filters. Pulley coupling scheme is used to selectively couple to one of the radial modes of the microdisk and also to achieve a strong coupling. A first-order tunable narrowband filter based on the microdisk-based delay line is experimentally demonstrated in an SOI platform, which shows a tunable bandwidth from 4.1 GHz to 0.47 GHz with an overall size of 0.05 mm². Finally, to address the challenges for the resonator-based delay lines encountered in the SOI platform, we propose to vertically integrate silicon nitride to the SOI platform, which can potentially have significantly lower propagation loss and higher power handling capability. High-Q silicon nitride microresonators are demonstrated; especially, microresonators with a 16 million intrinsic Q and a moderate size of 240 µm radius are realized, which is one order of magnitude improvement compared to what can be achieved in the SOI platform using the same fabrication technology. We have also successfully grown silicon nitride on top of SOI and a good coupling has been achieved between the silicon nitride and the silicon layers.

Extreme environments pose major obstacles for electronics in the form of extremely wide temperature ranges and hazardous radiation. The most common mitigation procedures involve extensive shielding and temperature control or complete displacement from the environment with high costs in weight, power, volume, and performance. There has been a shift away from these solutions and towards distributed, in-environment electronic systems. However, for this methodology to be viable, the requirements of heavy radiation shielding and temperature control have to be lessened or eliminated. This work gained new understanding of the best practices in analog circuit design for extreme environments. Major accomplishments included the over-temperature -180 C to +120 C and radiation validation of the SiGe Remote Electronics Unit, a first of its kind, 16 channel, sensor interface for unshielded operation in the Lunar environment, the design of two wide-temperature (-180 C to +120 C), total-ionizing-dose hardened, wireline transceivers for the Lunar environment, the low-frequency-noise characterization of a second-generation BiCMOS process from 300 K down to 90 K, the explanation of the physical mechanisms behind the single-event transient response of cascode structures in a 45 nm, SOI, radio-frequency, CMOS technology, the analysis of the single-event transient response of differential structures in a 32 nm, SOI, RF, CMOS technology, and the prediction of scaling trends of single-event effects in SOI CMOS technologies.

Multi-layered electronic packages increase in complexity with demands for functionality. Interfacial delamination remains a prominent failure mechanism due to mismatch of coefficient of thermal expansion (CTE). Numerous studies have investigated interfacial cracking in microelectronic packages using fracture mechanics, which requires knowledge of starter crack locations and crack propagation paths. Cohesive zone theory has been identified as an alternative method for modeling crack propagation and delamination without the need for a pre-existing crack. In a cohesive zone approach, traction forces between surfaces are related to the crack tip opening displacement and are governed by a traction-separation law. Unlike traditional fracture mechanics approaches, cohesive zone analyses can predict starter crack locations and directions or simulate complex geometries with more than one type of interface. In a cohesive zone model, cohesive zone elements are placed along material interfaces. Parameters that define cohesive zone behavior must be experimentally determined to be able to predict delamination propagation in a microelectronic package. The objective of this work is to study delamination propagation in a copper/mold compound interface through cohesive zone modeling. Mold compound and copper samples are fabricated, and such samples are used in experiments such as four-point bend test and double cantilever beam test to obtain the cohesive zone model parameters for a range of mode mixity. The developed cohesive zone elements are then placed in a small-outline integrated circuit package model at the interface between an epoxy mold compound and a copper lead frame. The package is simulated to go through thermal profiles associated with the fabrication of the package, and the potential locations for delamination are determined. Design guidelines are developed to reduce mold compound/copper lead frame interfacial delamination.