Tang Tze Yeung Eric. / Thesis submitted in: July 2003. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2004. / Includes bibliographical references (leaves 69-75). / Abstracts in English and Chinese. / ABSTRACT --- p.II / ACKNOWLEDGMENT --- p.II / Chapter 1 --- INTRODUCTION --- p.1 / Chapter 1.1 --- Embedded System --- p.1 / Chapter 1.2 --- Embedded Processor --- p.1 / Chapter 1.3 --- Embedded System Design --- p.3 / Chapter 1.3.1 --- Current Embedded System Design Challenges --- p.3 / Chapter 1.3.2 --- Embedded System Design Trend --- p.4 / Chapter 1.4 --- Efficient Software Development for Microprocessor --- p.8 / Chapter 1.4.1 --- Efficient Software Development Methodology --- p.8 / Chapter 1.5 --- Thesis Organization --- p.10 / Chapter 2 --- SOURCE CODE OPTIMIZATION --- p.11 / Chapter 2.1 --- Source Code Optimization Strategy --- p.11 / Chapter 2.2 --- Source Code Transformations --- p.12 / Chapter 2.2.1 --- Strength Reduction --- p.12 / Chapter 2.2.2 --- Function Inlining --- p.13 / Chapter 2.2.3 --- Table Lookup --- p.13 / Chapter 2.2.4 --- Loop Transformations --- p.13 / Chapter 2.2.5 --- Software Pipelining --- p.15 / Chapter 2.2.6 --- Register Allocation --- p.17 / Chapter 2.3 --- Case Study: Source Code Optimization on the StrongARM (SA1110) Platform --- p.18 / Chapter 2.3.1 --- StrongARM architecture --- p.18 / Chapter 2.3.2 --- StrongARM pipeline hazard illustration --- p.20 / Chapter 2.3.3 --- Source Code Optimization on StrongARM --- p.21 / Chapter 2.3.4 --- Instruction Set Optimization of StrongARM --- p.27 / Chapter 2.4 --- Conclusion --- p.32 / Chapter 3 --- FLOAT-TO-FIXED OPTIMIZATION --- p.33 / Chapter 3.1 --- Introduction to Fixed-point --- p.34 / Chapter 3.1.1 --- Fixed-point representation --- p.34 / Chapter 3.1.2 --- Fixed-point implementation --- p.35 / Chapter 3.1.3 --- Mathematical functions implementation --- p.38 / Chapter 3.2 --- Case Study: Fingerprint Minutiae Extraction Algorithms on the Strong ARM platform --- p.41 / Chapter 3.2.1 --- Fingerprint Verification Overview --- p.42 / Chapter 3.2.2 --- Fixed-point Implementation of Fingerprint Minutiae Extraction Algorithm --- p.49 / Chapter 3.2.3 --- Experimental Results --- p.51 / Chapter 3.3 --- Conclusion --- p.56 / Chapter 4 --- DOMAIN SPECIFIC OPTIMIZATION --- p.57 / Chapter 4.1 --- Case Study: Font Rasterization on the Strong ARM platform --- p.57 / Chapter 4.1.1 --- Outline Font --- p.57 / Chapter 4.1.2 --- Font Rasterization --- p.59 / Chapter 4.1.3 --- Experiments --- p.63 / Chapter 4.2 --- Conclusion --- p.66 / Chapter 5 --- CONCLUSION --- p.67 / BIBLIOGRAPHY --- p.69

A relatively recent development in the late 1980s in processors has been the superscalar processor. Superscalar processors use multiple pipelines in an attempt to achieve higher performance than previous generations of processors. Having multiple pipelines makes it possible to execute more than one instruction per cycle. However, since instructions are not independent of one another, but are interdependent, there is no guarantee that any given sequence of instruction will take advantage of the wider pipeline. One major factor that governs the ability of a processor to discover parallel instructions is the processor's mechanism for decoding and executing instruction. For superscalar processors with the central window design, the number of parallel instructions discovered is dependent on the size of the window. With a large window, the probability that the processor can find more parallel instructions is higher because there are more instruction to choose from. However, the larger the window the longer the critical path and thus lower clock speed. The major theme of this thesis is to find ways to have a large instruction window but still have clock speed comparable to a small instruction window processor. One way to achieve this is to apply the idea of memory interleaving to the processor's instruction window or reservation station design. With interleaving, there are multiple small instruction windows instead of one large window. In the first cycle the first window is used, and the second window is used in the second clock cycle. After all windows are used, the processor returns to the first window. Therefore with the interleaved design only a small portion of the whole instruction window is active at one time. In this way, there can be a large virtual window. Furthermore since the size of individual window is kept small, the clock speed is not affected. The rest of this thesis will explain how this interleaved instruction window scheme works and also list some simulation results to show its performance. / Graduation date: 1997

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This thesis presents novel aspects of the design of Strategist, a microprocessor designed to support efficient rewriting-based computation and pattern matching in particular. After introducing the architecture of Strategist, three of its novel features are described: predicate compression, quadrature low-swing logic and a high radix, bufferless on-chip network design. Predicate compression allows processors which make use of predicated execution to save a significant amount of code space, issue bandwidth and energy, by compressing predicate register references in a way that makes use of their peculiar temporal distributions. Quadrature low-swing logic is a new logic style which allows significant improvements in efficiency for realising both simple and complex logic functions in modern semiconductor processes. Finally, we describe a high radix on-chip network design which allows low-latency communication to be sustained under high traffic loads despite its simple, bufferless routers. Taken together, these features enable the design of more efficient special purpose multi-core processors, such as Strategist.

This dissertation investigates diverse techniques to support multithreading in modern high performance processors. The mechanisms studied expand the architecture of a high performance superscalar processor to control efficiently the interaction between software-controlled and hardware-controlled multithreading. Additionally, dynamic speculative mechanisms are proposed to exploit thread-level-parallelism (TLP) and instruction-level-parallelism (ILP) on a Simultaneous Multithreading (SMT) architecture. First, the hybrid multithreaded execution model is discussed. This model combines software-controlled multithreading with hardware support for efficient context switching and thread scheduling. A thread scheduling technique called set scheduling is introduced and its impact on the overall performance is described. An analytical model of the hybrid multithreaded execution is developed and validated by simulation. Through stochastic simulation, we find that the application of the hybrid multithreaded execution model results in higher processor utilization than traditional software-controlled multithreading. Next, in the main part of this dissertation, a new architecture is proposed: the Dynamic Simultaneous Multithreading (DSMT) processor. In this architecture, multiple threads are identified and created speculatively at runtime without compiler help. Subsequently, a SMT processor core executes those threads. The performance of a DSMT processor was evaluated with a new execution-driven simulator developed specifically for the purpose. Our experimental results based on simulation show that DSMT architecture has very good potential to improve SMT processor's performance when there is only a single task available for execution. / Graduation date: 2003

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