The increasingly more sophisticated systems that are nowadays implemented on a single chip are placing stringent requirements on the test industry. New test strategies, equipment, and methodologies need to be developed to sustain the constant increase in demand for consumer and communication electronics. Techniques for built-in-self-test (BIST) and design-for-test (DFT) strategies have been proven to offer more feasible and economical testing solutions. / Previous works have been conducted to perform on-chip testing, characterization, and measurement of signals and components. The current thesis advances those techniques on many levels. In terms of performance, an increase of more than an order of magnitude in speed is achieved. 70-GHz (effective sampling) on-chip oscilloscope is reported, compared to 4-GHz and 10-GHz ones in previous state-of-the-art implementations. Power dissipation is another area where the proposed work offer a superior solution compared to previous alternatives. All the proposed circuits do not exceed a few milliWatts of power dissipation, while performing multi-GHz high-speed signal capture at a medium resolution. Finally, and possibly most importantly, all the proposed circuits for test rely on a different form of signal processing; the time-based approach. It is believed that this approach paves the path to a lot of new techniques and circuit design skills that can be investigated more deeply. As an integral part of the time-based processing approach for GHz signal capture, this thesis verifies the advantages of using time amplification. The use of such amplification in the time domain is materialized with experimental results from three specific integrated circuits achieving different tasks in GHz high-speed in-situ signal measurement and characterization. Advantages of using such time-based approach techniques, when combined with the use of a front-end time amplifier, include noise immunity, the use of synthesizable digital cells, and circuit building blocks that track the technology scaling in terms of area and speed.

FFT-based tests (e.g. gain, distortion, SNR, etc.) from a device-under-test (DUT) exhibit normal distributions when the measurement is repeated many times. Hence, a statistical approach to evaluate the accuracy of these measurements is traditionally applied. The noise in a DSP-based mixed-signal test system severely limits its measurement accuracy. Moreover, in high-speed sampled-channel applications the jitter-induced noise from the DUT and test equipment can severely impede accurate measurements. / A new digitizer architecture and post-processing methodology is proposed to increase the measurement accuracy of the DUT and the test equipment. An optimal digitizer design is presented which removes any measurement bias due to noise and greatly improves measurement repeatability. Most importantly, the presented system improves accuracy in the same test time as any conventional test. / An integrated mixed-signal test core was implemented in TSMC's 0.18 mum mixed-signal process. Experimental results obtained from the mixed-signal integrated test core validate the proposed digitizer architecture and post processing technique. Bias errors were successfully removed and measurement variance was improved by a factor of 5.

Nürnberg, University, Diss., 2004--Erlangen.

Techn. Universiẗat, Diss., 2004--Darmstadt.

Zugl.: München, Techn. Univ., Diss., 2009

Thesis (Ph. D.)--Oregon State University, 2008. / Printout. Includes bibliographical references (leaves 79-82). Also available on the World Wide Web.

Atualmente, os sistemas eletrônicos integrados seguem o paradigma do projeto baseado em núcleos de hardware. Além de núcleos digitais, tais sistemas podem incluir núcleos analógicos, que, neste caso, dominam os requisitos de teste, como tempo de teste e número adicional de pinos. Consequentemente, há um aumento do custo total de manufatura do dispositivo. O presente trabalho propõe o uso de técnicas de autoteste integrado (BIST) analógico, baseado no reuso de núcleos digitais presentes no mesmo sistema, com objetivo de reduzir os custos relativos ao teste do sistema. Além disso, uma estratégia satisfatória requer um adequado planejamento de teste, de forma a melhor explorar as possibilidades de teste simultâneo de mais de um núcleo e o escalonamento do teste de cada um destes, diminuindo custos associados ao teste. Adaptando uma ferramenta computacional voltada ao planejamento de sistemas compostos exclusivamente de núcleos digitais para o universo dos sistemas mistos e considerando a possibilidade do uso de BIST, pode-se avaliar o impacto da estratégia proposta em termos de tempo de teste, acréscimo de área em virtude das estruturas de teste e pinos extras. Restrições de dissipação de potência também são consideradas. Para validação das hipóteses levantadas, sistemas mistos foram descritos a partir de benchmarks industriais e acadêmicos puramente digitais, através da inclusão de núcleos analógicos. Os resultados obtidos através de simulações com a ferramenta apontam para uma redução no tempo de teste e otimização de custos de pinos e área, além da redução no custo de equipamentos automatizados de teste (ATE), para o caso de teste de produção. Com isso, uma redução no custo total do procedimento de teste de tais sistemas pode ser alcançada. / Currently, integrated electronic systems follow the core-based design paradigm. Such systems include not only digital circuits as internal blocks, but also analog circuits, which dominate test resources, such as testing time, extra pins and overhead area, thus increasing the total manufacture cost of these devices. The present work proposes the application of analog Built-in Self Test (BIST) techniques based on the reuse of available digital cores within the same integrated system, aiming to reduce the test costs of the analog cores. Moreover, a satisfactory strategy requires an adequate test planning, so that the design space is better explored. By adapting a software tool, which was originally designed for test planning of exclusively digital SOC, to consider analog cores, as well as the possibility of BIST, one can evaluate the impact of the proposed strategy in terms of test application time, area overhead due to test structures added and extra pins. Power dissipation restrictions may also be taken into account. In order to validate the hypotheses considered, mixed-signal systems are described from digital industrial and academic benchmarks, just adding analog cores. Through simulation with the adapted tool, the obtained results point to a decrease in the system test time, as well as a reduction in the cost of Automatic Test Equipment (ATE), in case of a production test. Thus, a reduction in the overall cost of the test procedure for such devices can be achieved.

Atualmente, os sistemas eletrônicos integrados seguem o paradigma do projeto baseado em núcleos de hardware. Além de núcleos digitais, tais sistemas podem incluir núcleos analógicos, que, neste caso, dominam os requisitos de teste, como tempo de teste e número adicional de pinos. Consequentemente, há um aumento do custo total de manufatura do dispositivo. O presente trabalho propõe o uso de técnicas de autoteste integrado (BIST) analógico, baseado no reuso de núcleos digitais presentes no mesmo sistema, com objetivo de reduzir os custos relativos ao teste do sistema. Além disso, uma estratégia satisfatória requer um adequado planejamento de teste, de forma a melhor explorar as possibilidades de teste simultâneo de mais de um núcleo e o escalonamento do teste de cada um destes, diminuindo custos associados ao teste. Adaptando uma ferramenta computacional voltada ao planejamento de sistemas compostos exclusivamente de núcleos digitais para o universo dos sistemas mistos e considerando a possibilidade do uso de BIST, pode-se avaliar o impacto da estratégia proposta em termos de tempo de teste, acréscimo de área em virtude das estruturas de teste e pinos extras. Restrições de dissipação de potência também são consideradas. Para validação das hipóteses levantadas, sistemas mistos foram descritos a partir de benchmarks industriais e acadêmicos puramente digitais, através da inclusão de núcleos analógicos. Os resultados obtidos através de simulações com a ferramenta apontam para uma redução no tempo de teste e otimização de custos de pinos e área, além da redução no custo de equipamentos automatizados de teste (ATE), para o caso de teste de produção. Com isso, uma redução no custo total do procedimento de teste de tais sistemas pode ser alcançada. / Currently, integrated electronic systems follow the core-based design paradigm. Such systems include not only digital circuits as internal blocks, but also analog circuits, which dominate test resources, such as testing time, extra pins and overhead area, thus increasing the total manufacture cost of these devices. The present work proposes the application of analog Built-in Self Test (BIST) techniques based on the reuse of available digital cores within the same integrated system, aiming to reduce the test costs of the analog cores. Moreover, a satisfactory strategy requires an adequate test planning, so that the design space is better explored. By adapting a software tool, which was originally designed for test planning of exclusively digital SOC, to consider analog cores, as well as the possibility of BIST, one can evaluate the impact of the proposed strategy in terms of test application time, area overhead due to test structures added and extra pins. Power dissipation restrictions may also be taken into account. In order to validate the hypotheses considered, mixed-signal systems are described from digital industrial and academic benchmarks, just adding analog cores. Through simulation with the adapted tool, the obtained results point to a decrease in the system test time, as well as a reduction in the cost of Automatic Test Equipment (ATE), in case of a production test. Thus, a reduction in the overall cost of the test procedure for such devices can be achieved.

abstract: Time-interleaved analog to digital converters (ADCs) have become critical components in high-speed communication systems. Consumers demands for smaller size, more bandwidth and more features from their communication systems have driven the market to use modern complementary metal-oxide-semiconductor (CMOS) technologies with shorter channel-length transistors and hence a more compact design. Downscaling the supply voltage which is required in submicron technologies benefits digital circuits in terms of power and area. Designing accurate analog circuits, however becomes more challenging due to the less headroom. One way to overcome this problem is to use calibration to compensate for the loss of accuracy in analog circuits. Time-interleaving increases the effective data conversion rate in ADCs while keeping the circuit requirements the same. However, this technique needs special considerations as other design issues associated with using parallel identical channels emerge. The first and the most important is the practical issue of timing mismatch between channels, also called sample-time error, which can directly affect the performance of the ADC. Many techniques have been developed to tackle this issue both in analog and digital domains. Most of these techniques have high complexities especially when the number of channels exceeds 2 and some of them are only valid when input signal is a single tone sinusoidal which limits the application. This dissertation proposes a sample-time error calibration technique which bests the previous techniques in terms of simplicity, and also could be used with arbitrary input signals. A 12-bit 650 MSPS pipeline ADC with 1.5 GHz analog bandwidth for digital beam forming systems is designed in IBM 8HP BiCMOS 130 nm technology. A front-end sample-and-hold amplifier (SHA) was also designed to compare with an SHA-less design in terms of performance, power and area. Simulation results show that the proposed technique is able to improve the SNDR by 20 dB for a mismatch of 50% of the sampling period and up to 29 dB at 37% of the Nyquist frequency. The designed ADC consumes 122 mW in each channel and the clock generation circuit consumes 142 mW. The ADC achieves 68.4 dB SNDR for an input of 61 MHz. / Dissertation/Thesis / Doctoral Dissertation Electrical Engineering 2017

Atualmente, os sistemas eletrônicos integrados seguem o paradigma do projeto baseado em núcleos de hardware. Além de núcleos digitais, tais sistemas podem incluir núcleos analógicos, que, neste caso, dominam os requisitos de teste, como tempo de teste e número adicional de pinos. Consequentemente, há um aumento do custo total de manufatura do dispositivo. O presente trabalho propõe o uso de técnicas de autoteste integrado (BIST) analógico, baseado no reuso de núcleos digitais presentes no mesmo sistema, com objetivo de reduzir os custos relativos ao teste do sistema. Além disso, uma estratégia satisfatória requer um adequado planejamento de teste, de forma a melhor explorar as possibilidades de teste simultâneo de mais de um núcleo e o escalonamento do teste de cada um destes, diminuindo custos associados ao teste. Adaptando uma ferramenta computacional voltada ao planejamento de sistemas compostos exclusivamente de núcleos digitais para o universo dos sistemas mistos e considerando a possibilidade do uso de BIST, pode-se avaliar o impacto da estratégia proposta em termos de tempo de teste, acréscimo de área em virtude das estruturas de teste e pinos extras. Restrições de dissipação de potência também são consideradas. Para validação das hipóteses levantadas, sistemas mistos foram descritos a partir de benchmarks industriais e acadêmicos puramente digitais, através da inclusão de núcleos analógicos. Os resultados obtidos através de simulações com a ferramenta apontam para uma redução no tempo de teste e otimização de custos de pinos e área, além da redução no custo de equipamentos automatizados de teste (ATE), para o caso de teste de produção. Com isso, uma redução no custo total do procedimento de teste de tais sistemas pode ser alcançada. / Currently, integrated electronic systems follow the core-based design paradigm. Such systems include not only digital circuits as internal blocks, but also analog circuits, which dominate test resources, such as testing time, extra pins and overhead area, thus increasing the total manufacture cost of these devices. The present work proposes the application of analog Built-in Self Test (BIST) techniques based on the reuse of available digital cores within the same integrated system, aiming to reduce the test costs of the analog cores. Moreover, a satisfactory strategy requires an adequate test planning, so that the design space is better explored. By adapting a software tool, which was originally designed for test planning of exclusively digital SOC, to consider analog cores, as well as the possibility of BIST, one can evaluate the impact of the proposed strategy in terms of test application time, area overhead due to test structures added and extra pins. Power dissipation restrictions may also be taken into account. In order to validate the hypotheses considered, mixed-signal systems are described from digital industrial and academic benchmarks, just adding analog cores. Through simulation with the adapted tool, the obtained results point to a decrease in the system test time, as well as a reduction in the cost of Automatic Test Equipment (ATE), in case of a production test. Thus, a reduction in the overall cost of the test procedure for such devices can be achieved.