<p>This Bachelor thesis is a pre-study of the possibilities of using programmable logic in the purpose to enable fast trigger based data communication. Triggerbased data communication is in this case referred to a context where the processed data is stored and examined so when the trig situation appears the data should be able read out to a computer for evaluating. The purpose of this thesis is to find difficult and time consuming elements but also to find elements that is well suited for implementation in programmable logic. The work should also support further development and verification of trig functionalities and additional hardware. This with the intent of constructing an Ethernet based oscilloscope.</p><p>The result of this thesis is a conclusion that programmable logic is well suited for many of the implemented logic function</p>

This Bachelor thesis is a pre-study of the possibilities of using programmable logic in the purpose to enable fast trigger based data communication. Triggerbased data communication is in this case referred to a context where the processed data is stored and examined so when the trig situation appears the data should be able read out to a computer for evaluating. The purpose of this thesis is to find difficult and time consuming elements but also to find elements that is well suited for implementation in programmable logic. The work should also support further development and verification of trig functionalities and additional hardware. This with the intent of constructing an Ethernet based oscilloscope. The result of this thesis is a conclusion that programmable logic is well suited for many of the implemented logic function

In this work I describe digital predistortion in baseband used for amplifier linearization. Non-linearity is one of the worst disadvantages of Power amplifiers and decreasing of its is useful from many reasons. Work examines system which contains: Data source, which is represented by QPSK or OFDM modulator, predistorter, Power amplifier (model of non-linearity) and unit used to update coeficients for predistorter adaptation. System is simulated in MATLAB and Xilinx (simulation by ModelSim). Results are compared, described and commented.

The thesis deals with the issue of implementing a PCI interface controller utilizing the FPGA technology. It describes the design and the implementation of a PCI communication card, which is used to control servomotors in cutting machines. In the thesis, the steps taken in designing and implementation of hardware and software parts of the communication card are discussed. The result of the thesis is a functional piece of equipment, which is to be manufactured.

<p>In the last three decades we have witnessed a remarkable development in the area of integrated circuits. From small logic devices containing some hundred transistors to modern processors containing several tens of million transistors. However, power consumption has become a real problem and may very well be the limiting factor of future development. Designing for low power is therefore increasingly important. To accomplice an efficient low power design, accurate power estimation at early design stage is essential. The aim of this thesis was to set up a power estimation flow to estimate the power consumption at early design stage. The developed flow spans over both RTL- and gate-level incorporating Mentor Graphics Modelsim (RTL-level simulator), Cadence PKS (gate- level synthesizer) and own developed power estimation tools. The power consumption is calculated based on gate-level physical information and RTL- level toggle information. To achieve high estimation accuracy, real node annotations is used together with an own developed on-chip wire model to estimate node voltage swing. </p><p>Since the power estimation may be very time consuming, the flow also includes support for low power design iteration. This gives efficient power estimation speedup when concentrating on smaller sub- parts of the design.</p>

In the last three decades we have witnessed a remarkable development in the area of integrated circuits. From small logic devices containing some hundred transistors to modern processors containing several tens of million transistors. However, power consumption has become a real problem and may very well be the limiting factor of future development. Designing for low power is therefore increasingly important. To accomplice an efficient low power design, accurate power estimation at early design stage is essential. The aim of this thesis was to set up a power estimation flow to estimate the power consumption at early design stage. The developed flow spans over both RTL- and gate-level incorporating Mentor Graphics Modelsim (RTL-level simulator), Cadence PKS (gate- level synthesizer) and own developed power estimation tools. The power consumption is calculated based on gate-level physical information and RTL- level toggle information. To achieve high estimation accuracy, real node annotations is used together with an own developed on-chip wire model to estimate node voltage swing. Since the power estimation may be very time consuming, the flow also includes support for low power design iteration. This gives efficient power estimation speedup when concentrating on smaller sub- parts of the design.

In this exam project the investigation has been done to determine, which profits that can be made by switching an internal bus between two chips, one FPGA and a processor, to an internal bus implemented on only one chip, System on Chip. The work is based on measurements made in real time in Xilinx’s development tools on different buses, AXI4 and AXI4-Light connected to AXI3. The port that is used is FPGA’s own GP-port. Besides measuring the time of transactions also physical aspects have been investigated in this project: space, costs and time. Based on those criteria a comparison to the original construction was made to determine which benefits that can be achieved. The work has shown a number of results that are in comparison with the original construction. The System on Chip has turned out to be a better solution in most cases. When using the AXI4-Light-bus the benefits were not as obvious. Cosmic radiation, temperature or humidity are beyond the scope of this investigation. In the work the hypothetic deductive method has been used to prove that the System on Chip is faster than the original design. In this method three statements must be set up against each other; one statement that ought to be true, one statement that is a contradiction and a conclusion of what is proved. The pre-study pointed out that the System on Chip is a faster solution than the original construction. The method is useful since it proves that the pre-study is comparable to the measured results. / I detta examensarbete har undersökningar gjorts för att fastställa vilka vinster som går att göra genom att byta en internbuss mellan två chip, en FPGA och en processor, mot en intern buss implementerat på ett enda chip, System on Chip. Arbetet bygger på mätningar gjorda i realtid i Xilinx utvecklingsverktyg på olika bussar, AXI4 och AXI4‑Lite som är kopplade internt mot AXI3. Den port som används är FPGAs egen GP‑port. Förutom att mäta överföringshastigheterna, har även fysiska aspekter som utrymme, kostnader och utvecklingstid undersökts. Utifrån dessa kriterier har en jämförelse gjorts med den befintliga konstruktionen för att fastställa vilka vinster som går att uppnå. Arbetet har resulterat i ett antal resultat som är ställda mot de förutsättningar som fanns i den ursprungliga lösningen. I de flesta fall visar resultatet att ett System on Chip är en bättre lösning. De fall som var tveksamma var vid viss typ av överföring med AXI4‑Lite bussen. I arbetet har inte undersökning av kosmisk strålning, temperatur eller luftfuktighet betraktas. I arbetet med att försöka att bevisa att ett System on Chip är snabbare än den ursprungliga uppsättningen har utvecklingsmetoden hypotetisk deduktiv använts. Denna metod bygger på att man från början sätter upp ett påstående, som man förutsätter är sant, följt av en konjunktion, som inte får inträffa, för att slutligen dra en slutsats, som konstaterar fakta. Eftersom fakta som lästes in i början av arbetet pekade på att ett System on Chip var en snabbare och billigare lösning kändes metoden användbar. Under arbetets gång har det visat sig vara en bra metod som också ger ett resultat där sannolikheten för att det är en snabbare lösning ökar. Däremot säger inte metoden att det är helt säkert att den i alla situationer är bättre, vilket kan ändras om man använder andra förutsättningar eller tar med andra aspekter.

Quadrature modulator (demodulator) is used in transmitting (receiving) part of many devices. Unwanted imbalance can influence amplitude, phase or DC offset of modulator (demodulator). Correction of imbalance was a main subject of thesis. Simulations of these methods were created in MATLAB and results were compared. Basics of methods were implement on programmable logic field by program Xilinx ISE. Development kit V2MB1000 with analogue board Memec P160 was chosen for this purpose. In the last part were compare simulation results with practical measurement.

The primary outcome of this thesis is found in three contributions. First, we developed an automatic converter from the cube representation of incompletely specified multiple-output Boolean function, given in Espresso format, to VHDL. The converter is designed specifically for updating functions of Feedback Shift Register (FSRs) in the Galois configuration, namely it reads in the description of a combinatorial function and adds register stages to the appropriate positions. The converter can handle both, Linear and Non-Linear feedback Shift Registers. The second contribution is modifying the automatic converter to design a tool which gives the user the opportunity to see the hardware characteristics of its circuit quickly from the espresso format of its design. The third contribution is applying the resulting converter to evaluate the results of the CRC generation algorithm presented in [6]. We computed the hardware characteristics such as area, timing and power dissipation on most popular CRCs in ASIC and FPGA technologies. Furthermore, we introduced a simple interface used to provide the user a good estimation of the power diagram during the executing time which is similar to probing the current of the circuit.