Thesis (M.S. in E.E.)--School of Electrical and Computer Engineering, Georgia Institute of Technology, 2004. Directed by David V. Anderson. / Includes bibliographical references (leaves 55-56).

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Typescript (photocopy). / Digitized by Kansas Correctional Industries

Zhao, Yinsheng. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2011. / Includes bibliographical references (leaves 90-93). / Abstracts in English and Chinese. / ABSTRACT --- p.I / 摘要 --- p.II / CONTENTS --- p.III / LIST OF FIGURES --- p.V / LIST OF TABLES --- p.VII / ACKNOWLEDGEMENT --- p.VIII / Chapter CHAPTER 1 --- INTRODUCTION --- p.1 / Chapter 1.1 --- MOTIVATION --- p.1 / Chapter 1.2 --- ORGANIZATION OF THE THESIS --- p.5 / Chapter CHAPTER 2 --- BASIC THEOREMS OF DELTA SIGMA ADC --- p.6 / Chapter 2.1 --- INTRODUCTION TO SAMPLING TECHNIQUE --- p.6 / Chapter 2.2 --- DELTA-SIGMA ORDER & NOISE-SHAPING ORDER --- p.8 / Chapter 2.2.1 --- FIRST ORDER CLELTA-SIGMA MODULATOR --- p.8 / Chapter 2.2.2 --- HIGH ORDER DELTA-SIGMA MODULATOR --- p.11 / Chapter 2.3 --- CHOPPER-STABILIZATION TECHNIQUE --- p.13 / Chapter 2.4 --- MIRRORED INTEGRATOR --- p.16 / Chapter 2.5 --- PERFORMANCE METRICS --- p.18 / Chapter 2.5.1 --- SIGNAL TO NOISE RATIO (SNR) --- p.18 / Chapter 2.5.2 --- SIGNAL TO NOISE AND DISTORTION RATIO (SNDR) --- p.19 / Chapter 2.5.3 --- DYNAM IC RANGE --- p.19 / Chapter 2.5.4 --- EFFECTIVE NUMBER OF BITS --- p.19 / Chapter 2.5.5 --- "OVERLOAD LEVER, XOL" --- p.19 / Chapter 2.6 --- CONCLUSION --- p.20 / Chapter CHAPTER 3 --- NON-IDEALITIES IN SYSTEM MODELING --- p.21 / Chapter 3.1 --- CLOCK JITTER --- p.21 / Chapter 3.2 --- NON-IDEAL EFFECT OF OPERATIONAL AMPLIFIER --- p.23 / Chapter 3.2.1 --- FINITE OPEN-LOOP GAIN --- p.23 / Chapter 3.2.2 --- FINITE BANDWIDTH AND SLEW-RATE --- p.24 / Chapter 3.3 --- CAPACITOR RATIO ERROR --- p.26 / Chapter 3.4 --- THERMAL NOISE --- p.27 / Chapter 3.5 --- SWITCH CHARGE INJECTION ERROR --- p.30 / Chapter 3.6 --- CONCLUSION --- p.34 / Chapter CHAPTER 4 --- A CHOPPER-STABILIZED HIGH-PASS DELTA-SIGMA MODULATOR IN 1.8V 0.18MM CMOS --- p.35 / Chapter 4.1 --- STRUCTURE SELECTION --- p.35 / Chapter 4.2 --- SYSTEM MODELING AND PARAMETER SELECTION --- p.38 / Chapter 4.3 --- CIRCUIT IMPLEMENTATION --- p.42 / Chapter 4.3.1 --- OPERATIONAL AMPLIFIER --- p.42 / Chapter 4.3.2 --- QUANTIZER --- p.44 / Chapter 4.3.3 --- FREQUENCY DIVIDER --- p.47 / Chapter 4.3.4 --- OVERALL CIRCUIT --- p.48 / Chapter 4.4 --- LAYOUT IMPLEMENTATION --- p.50 / Chapter 4.4.1 --- LAYOUT SYMMETRIC TECHNIQUE --- p.50 / Chapter 4.4.2 --- CIRCUIT LAYOUT --- p.53 / Chapter 4.4.3 --- FLOOR PLANNING AND TOP LEVEL INTER-CONNECT!ON --- p.56 / Chapter 4.5 --- MEASUREMENT RESULTS --- p.58 / Chapter CHAPTER 5 --- A LOW-POWER CHOPPER-STABILIZED DELTA-SIGMA MODULATOR IN 1.2V0.18MM CMOS --- p.63 / Chapter 5.1 --- STRUCTURE SELECTION --- p.63 / Chapter 5.2 --- SYSTEM MODELING AND PARAMETER SELECTION --- p.67 / Chapter 5.3 --- CIRCUIT IMPLEMENTATION --- p.70 / Chapter 5.3.1 --- OPERATIONAL AMPLIFIER --- p.70 / Chapter 5.3.2 --- QUANTIZER --- p.73 / Chapter 5.3.3 --- LARGE DELAY GENERATION --- p.73 / Chapter 5.3.4 --- OVERALL CIRCUIT --- p.75 / Chapter 5.4 --- SIMULATION RESULTS --- p.77 / Chapter CHAPTER 6 --- DECIMATION FILTER DESIGN --- p.79 / Chapter 6.1. --- THE WHOLE VIEW OF DECIMATION FILTER --- p.79 / Chapter 6.2. --- THE DECIMATION FILTER IN SIMULINK --- p.80 / Chapter 6.2.1 --- SINE FILTER DESIGN --- p.80 / Chapter 6.2.2 --- HALF-BAND FILTER DESIGN --- p.82 / Chapter CHAPTER 7 --- CONCLUSIONS AND FUTURE WORKS --- p.88 / Chapter 7.1. --- CONCLUSIONS --- p.88 / Chapter 7.2. --- FUTURE WORKS --- p.89 / REFERENCES --- p.90 / PUBLICATION --- p.93

Thesis (Ph. D.)--Oregon State University, 2007. / Printout. Includes bibliographical references (leaves 76-78). Also available on the World Wide Web.

Delta-sigma modulators are currently a very popular technique for making high-resolution analog-to-digital converters (ADCs) and digital-to-analog converters (DACs). These oversampled data converters have several advantages over conventional Nyquist-rate converters, including an insensitivity to many analog component imperfections, a simpler antialiasing filter and reduced accuracy requirements in the sample and hold. A recent development in the realm of delta-sigma-based ADC and DAC systems is the use of multilevel (as opposed to binary) quantization. This development owes its existence to the discovery of a variety of techniques which cause linearity errors of the embedded multilevel DAC to be attenuated in the frequency band of interest. This thesis presents several methods for shaping the DAC element mismatch error and reducing the dynamic error in the band of interest. To demonstrate the effectiveness of the proposed algorithms, a current-mode unit element DAC is designed and used as a test bed. Both theoretical analysis and experimental results show that these methods can greatly attenuate the noise in the band of interest. The methods presented in this thesis will allow high performance, high-frequency wideband delta-sigma modulators to be constructed. / Graduation date: 1998

This dissertation investigates the constraints which arise when switched-capacitor (SC) delta-sigma modulators are designed for low-voltage operation, targeting also low power dissipation, and proposes methods of improving the performance and optimizing for low power dissipation. This is accomplished by identifying critical elements whose performance can lead to increased power dissipation, as well as the fundamental limitations of available analog circuit techniques. A prototype was designed and fabricated, which reflected these findings, and therefore exhibited good performance and nearly optimum power dissipation. One of the key performance parameters is the dc gain of the amplifier in the first stage; it should be high. This is necessary for high linearity and low quantization noise leakage. In low-voltage operation, it may become impractical to use conventional topologies employing cascoding techniques (e.g., folded-cascode) which provide high gain in one single stage. Rather, cascaded structures have to be used. The disadvantage of the latter is the necessity for frequency compensation which results in increased power dissipation. Hence, another objective of this work is to exploit techniques which compensate for the open-loop gain characteristic of the amplifier (dc gain and nonlinearity), thus permitting the utilization of single-stage low-gain topologies. Predictive correlated double sampling is one of such techniques and is analyzed in detail. / Graduation date: 1998

Graduation date: 1994

Graduation date: 1993